PCB科技 - 如何在PCB設計中减少雜訊和電磁干擾

如何减少雜訊和電磁干擾 PCB設計
您對减少譟音和電磁干擾瞭解多少 PCB設計?
(1) Low-speed chips can be used instead of high-speed chips. 在關鍵位置使用高速晶片.
(2) A resistor can be connected in series to reduce the jump rate of the upper and lower edges of the control circuit.
(3) Try to provide some form of damping for relays, 等.
(4) Use the lowest frequency clock that meets the system requirements.
(5) The clock generator is as close as possible to the device using the clock. 石英晶體振盪器的外殼應接地.
(6) Enclose the clock area with a ground wire and keep the clock wire as short as possible.
(7) The I/O驅動電路盡可能靠近 印刷電路板, 讓它離開 印刷電路板 儘快. 訊號進入 印刷電路板 應進行篩選, 來自高雜訊區域的訊號也應進行濾波. 同時, 應使用一系列終端電阻器來减少訊號反射.
(8) The useless end of MCD should be connected to high, 或接地, 或定義為輸出端, 集成電路的一端應連接到電源地, 並且不應保持浮動.

(9) Do not leave the input terminal of the gate circuit that is not in use. 未使用的運算放大器的正極輸入端子接地, 負極輸入端子連接到輸出端子.
(10) As far as possible for the 印刷電路板, 使用45折線代替90折線，以减少高頻訊號的外部發射和耦合.
(11) The 印刷電路板 根據頻率和電流開關特性進行劃分, 雜訊分量和非雜訊分量之間的距離應更遠.
(12) Use single-point power and single-point grounding for single and double panels. 電源線和地線應盡可能厚. 如果經濟實惠, 使用多層板降低電源和接地的電容電感.
(13) The clock, 公共汽車, 晶片選擇訊號應遠離I/O線路和連接器.
(14) The analog voltage input line and reference voltage terminal should be as far away as possible from the digital circuit signal line, 尤其是時鐘.
(15) For A/D設備, 數位部分和類比部分寧願統一，也不願交叉.
(16) The clock line perpendicular to the I/O線的干擾比平行I線小/O線, 時鐘元件引脚遠離I/O電纜.
(17) The component pins should be as short as possible, 去耦電容器引脚應盡可能短.
(18) The key line should be as thick as possible, 兩側加保護地. 高速線路應短而直.
(19) Lines sensitive to noise should not be parallel to high-current, 高速開關線路.
(20) Do not route wires under the quartz crystal and under noise-sensitive devices.
(21) For weak signal circuits, 不要在周圍形成電流回路 低頻電路.
(22) Do not form a loop in the signal. 如果不可避免, 使回路面積盡可能小.
(23) One decoupling capacitor per integrated circuit. 必須在每個電解電容器上添加一個小型高頻旁路電容器.
(24) Use large-capacity tantalum capacitors or ju-cool capacitors instead of electrolytic capacitors for circuit charging and discharging energy storage capacitors. 使用管狀電容器時, 案件應被接地.