PCB部落格 - 高品質PCB板設計應注意庫存

合理的部件佈置是設計高品質產品的基本前提 PCB電路板佈局.
1 組成部分 佈局
組件的要求 佈局 主要包括安裝, 武力, 熱, 訊號, 和美學.
1.1. Installation
Refers to a series of basic requirements for the smooth installation of the circuit board into the chassis, 套管, 和特定應用中的插槽, 避免空間干擾、短路等事故, 並將指定的連接器保持在主機殼或外殼上的指定位置. 要求. 我在這裡不談細節.

1.2. Force
The circuit board should be able to withstand various external forces and vibrations during installation and work. 因此, 電路板應具有合理的形狀, and the positions of various holes (screw holes, special-shaped holes) on the board should be reasonably arranged. 通常地, 孔和板邊緣之間的距離應至少大於孔的直徑. 同時, 還應注意，由异形孔引起的板的薄弱部分也應具有足够的彎曲強度. 特別地, 直接從板上的設備外殼“延伸”出來的連接器應合理固定，以確保長期可靠性.
1.3. Heat
For high-power devices with serious heat generation, 除了確保散熱條件外, 還應注意將其放置在適當的位置. 尤其是在複雜的類比系統中, 應特別注意這些設備產生的溫度場對脆弱前置放大器電路的不利影響. 通常地, 功率非常大的部件應製成單獨的模塊, 它與信號處理電路之間應採取一定的熱隔離措施.
1.4. Signals
Signal interference is an important factor to be considered in PCB 佈局 設計. 幾個基本方面是：弱訊號電路與强訊號電路分離甚至隔離； 交流部分與直流部分分離； 高頻部分與低頻部分分離； 注意訊號線的方向； 這個 佈局 接地線； 量測.
1.5. Beautiful
It is not only necessary to consider the neat and orderly placement of components, 還要考慮到佈線的優美和流暢. 因為一般外行有時會強調前者, 為了片面地評估電路設計的利弊, 對於產品的形象, 當效能要求不苛刻時，應優先考慮前者. 然而, 在高性能場合, 如果必須使用雙面板, 電路板也封裝在其中, 它通常是看不見的, 首先要強調佈線的美觀. 下一節將詳細討論佈線的“美學”.

2. Wiring principles
Some anti-jamming measures not commonly found in the literature are detailed below. 考慮到在實際應用中, 特別是在產品試製中, 仍在使用大量雙面面板, 以下內容主要針對雙面面板.

2.1. Wiring "Aesthetics"
When turning, 避免直角，並嘗試使用斜線或圓弧進行過渡. 接線應整齊有序, 集中佈置, 這不僅避免了不同性質訊號的相互干擾, 也便於檢查和修改. 對於數位系統, there is no need to worry about interference between signal lines (such as data lines and address lines) of the same camp, 但控制訊號，如read, 寫, 時鐘應隔離並用地線保護. When laying the ground on a large area (discussed further below), try to keep a reasonable and equal distance between the ground wire (in fact, it should be the ground "surface") and the signal wire, 在防止短路和洩漏的前提下，儘量靠近. 對於弱電系統, 接地線和電源線應盡可能靠近. 對於使用表面安裝組件的系統, 訊號線應該一直到前面.

2.2. Ground wire arrangement
There are many discussions on the importance and 佈局 文獻中的地線原理, 但仍缺乏對地線的詳細準確介紹 佈局 在實際中 PCB板s. My experience is that in order to improve the reliability of the system (rather than just making an experimental prototype), 地線怎麼強調都不為過, 尤其是在弱信號處理中. 為此目的, 我們必須不遺餘力地貫徹“大面積鋪路”的原則.

2.3. 電源線 佈局 and power filter
The general literature says that the power cord should be as thick as possible, 我不太同意. Only in the case of high power (the average power supply current may reach 1A in 1 second), it is necessary to ensure sufficient power line width (in my experience, 50mil per 1A current can meet the needs of most occasions). 如果只是為了防止訊號干擾，電源線的寬度並不重要. 即使, 有時較薄的電源線更有益. 電源的質量通常不主要取決於它, 但在電源的波動和疊加干擾中. 解决電源干擾的關鍵是濾波電容器! 如果您的應用程序對電能品質有嚴格要求, 不要吝嗇購買濾波電容器! 使用濾波電容器時應注意以下幾點：整個電路的功率輸入端應具有“總”濾波措施, 各種類型的電容器應相互匹配, “同樣不能少”, 至少J這不是壞事. 對於數位系統, at least 100uF electrolysis + 10uF tantalum + 0.1uF補丁 + 1nF patch . Higher frequency (100kHz) 100uF electrolysis + 10uF tantalum + 0.47uF patch + 0.1uF補丁. 交流模擬系統：直流和低頻模擬系統：1000uF|1000uF electrolysis + 10uF tantalum + 1uF patch + 0.1uF patch. 每個重要的晶片周圍都應該有一組濾波電容器. 對於數位系統, a 0.1uF補丁通常就足够了, 重要晶片或工作電流較大的晶片也應與10uF鉭晶片或1uF晶片連接, and the chip with operating frequency (CPU, crystal) should also be connected with 10nF| 470pF或1nF. 該電容器應盡可能靠近晶片的電源引脚，並盡可能直接連接, 越小越近. 片式濾波器電容器, the inner section (filter capacitor to chip power pins) should be as thick as possible. 如果多條細線可以並排使用就更好了. With the filter capacitor to provide a low (AC) impedance voltage source and suppress AC coupling interference, the power line outside the capacitor pin (referring to the section from the main power supply to the filter capacitor) is not so important, 線條寬度不需要太粗, 至少沒有必要為此佔用大量的電路板面積. 在一些類比系統中, 功率輸入還需要RC濾波網絡，以進一步抑制干擾, 而較薄的電源線有時只是充當RC濾波器中的電阻器, 這是有益的. 對於工作溫度變化範圍大的系統, 需要注意的是，在低溫下，鋁電解電容器的效能會降低，甚至失去濾波效果. 在這種情況下, 應使用合適的鉭電容器. 例如, 用100uF鉭代替470uF鋁 | 1000uF鋁, 或用22uF鉭片代替100uF鋁. 小心不要將鋁電解電容器放得離大功率加熱裝置太近.

3. 减少譟音和電磁干擾的經驗.
(1) High-speed chips are not needed if low-speed chips can be used, 在關鍵位置使用高速晶片.
(2) A resistor can be connected in series to reduce the transition rate of the upper and lower edges of the control circuit.
(3) Try to provide some form of damping for relays etc.
(4) Use a frequency clock that meets the system requirements.
(5) The clock generator is as close as possible to the device using the clock. 石英晶體振盪器外殼應接地.
(6) Circle the clock area with a ground wire, 並使時鐘線盡可能短.
(7) Use large-capacity tantalum capacitors or polycooled capacitors instead of electrolytic capacitors as circuit charge and discharge energy storage capacitors. 使用管狀電容器時, 案件應被接地.
(8) The useless end of MCD should be connected to high, 或接地, 或定義為輸出端. 應連接至電源接地的集成電路末端, 不應該讓它漂浮.
(9) Do not float the input terminals of the gate circuits that are not in use, 將未使用的運算放大器的正極輸入端子接地, 並將負極輸入端子連接到輸出端子.
(10) The printed board should try to use 45-fold lines instead of 90-fold lines to reduce the external emission and coupling of high-frequency signals.
(11) The printed board is divided according to frequency and current switching characteristics, 雜訊分量和非雜訊分量之間的距離應更遠.
(12) Single-point power supply and single-point grounding for single-panel and double-panel, 電源線和地線應盡可能厚. 如果經濟負擔得起, 使用多層板降低電源和接地的電容電感.
(13) The clock, 公共汽車, 晶片選擇訊號應遠離I/O線路和連接器.
(14) The analog voltage input line and the reference voltage terminal should be as far away as possible from the digital circuit signal line, 尤其是時鐘.
(15) For A/D設備, 數位部分和類比部分寧願統一，也不願移交.
(16) The clock line perpendicular to the I/O線的干擾比平行I線小/O線, 時鐘元件引脚遠離I/O電纜.
(17) The component pins should be as short as possible, 去耦電容器引脚應盡可能短.
(18) The key lines should be as thick as possible, 兩側加保護地. 高速線路應短而直.
(19) The line sensitive to noise should not be parallel to the high current, 高速開關線路.
(20) Do not route wires under the quartz crystal and under the devices that are sensitive to noise.
(21) For weak signal circuits, 不要在低頻電路周圍形成電流回路.
(22) Do not form a loop for any signal. 如果不可避免, 使回路面積盡可能小.
(23) One decoupling capacitor per integrated circuit. 應在每個電解電容器旁邊添加一個小型高頻旁路電容器.
(24) The signal entering the printed board should be filtered, 來自高雜訊區域的訊號也應進行濾波. 同時, 應使用串聯終端電阻的方法來减少訊號反射. I/O驅動電路盡可能靠近 PCB板, 這樣它就可以離開 印刷電路板 儘快.