p>Analysis of high frequency circuit in CAD
When the operating frequency is higher (about 2GHz), 訊號波長可以逐漸匹配設備大小. 片式電感的阻抗具有明顯的分佈特性, 那就是, 不同的參攷位置存在不同的阻抗. 高頻時, 器件的電路響應隨其尺寸和空間結構而變化. 傳統的阻抗量測參數不能準確反映實際電路的響應特性. 以手機射頻功率放大器電路為例, two high-frequency inductors (working frequency 1.9GHz) used for impedance matching are photolithographic thin-film inductors. If the laminated chip inductors (measuring instrument hp-4291b) with the same specifications and accuracy but significantly higher Q value are replaced, 電路的傳輸增益將下降近10%. 這表明電路的匹配狀態正在下降. 顯然，使用低頻分析方法無法準確解釋高頻的應用. 這不合適, 至少還不够, 注意帶L和q的片式電感的高頻分析.
電磁場理論在工程中常被用來分析具有分佈特性的高頻應用問題. 通常地, in the measurement of chip inductor by impedance analyzer (hp-4291b), 測量精度可以提高到0左右.1nh通過夾具補償和儀器校準, 這在理論上足以保證電路設計的精度要求. 然而, the problem that can not be ignored is that the measurement results at this time only reflect the parameter performance between the end electrode interfaces of the inductance device under the matching state (the measuring fixture is designed to accurately match), 但沒有反映電感器件的內部電磁分佈和外部電磁環境要求. 相同測試參數的電感器由於內電極結構的不同，其電磁分佈可能完全不同. 在高頻條件下, the actual circuit application environment (approximate matching, 密集安裝, PCB distribution influence) of chip inductors is often different from the test environment. 很容易產生各種複雜的近場反射, resulting in slight changes of actual response parameters (L, q). 射頻電路中的低電感, 這種影響不容忽視, 我們稱之為“分佈式影響”.
In the design of high-frequency circuit (including high-speed digital circuit), 考慮電路效能, 設備選擇和電磁相容性, the working performance of the actual circuit system is generally considered by means of network scattering analysis (s parameter), 信號完整性分析, 電磁模擬分析, 電路模擬分析, 等. 針對片式電感的“分佈影響”問題, 一種可行的解決方案是對電感器進行結構電磁模擬，準確選取相應的SPICE電路模型參數，作為電路設計的依據, 從而有效降低電感器件在高頻設計應用中的誤差影響. Most of the technical parameters of chip inductors produced by foreign (Japanese) main component enterprises contain s parameter, 可用於準確的高頻應用分析.
