PCB Technical - Why do high-speed PCBs need equal-length wiring?

Why do high-speed PCBs need equal-length wiring?
The effective establishment and maintenance window of high-speed signals is relatively small. To keep the data and control signals within the effective window, the difference in trace length between data, clock or data, and between control signals is very small. The specific allowable deviation can be obtained by calculating the time delay.
In fact, in general, sequential logic signals must meet the setup time and hold time and have a certain margin. As long as this condition is met, the signal may not be strictly equal in length. However, the actual situation is that for high-speed signals (such as DDR2, DDR3, FSB), it is impossible to know whether the timing meets the setup time and hold time requirements during the design (there are too many influencing factors, including the internal wiring and capacitance of the chip). The delay difference caused by the load must be considered, it is difficult to estimate the actual value through calculation), a controllable delay device must be set inside the chip (the delay is controlled by the register), and then the value of the register is scanned to try various delays. And by observing the signal (look at the waveform directly, and measure the setup and hold time) to determine the delay value to meet the setup time and hold time requirements. However, the same type of signal is generally only observed for one or a few of the signal lines. In order to make all the signals meet the timing requirements, it is necessary to specify that the same type of signal lines are all strictly equal in length.

The above is a high-speed parallel signal. For high-speed serial signals, if they are clocked, the clock and serial data must also meet the setup and hold time requirements, so the length must also be controlled.
Although some high-speed serial signals have a clock, this clock is not used to latch data but a reference clock with a lower frequency. Then the skew of data and clock and data between multiple channels can be much looser, and there is no need to wait strictly. Long, because the receiving chip can correctly find the start bit of each channel and use the PLL frequency multiplication and phase shift to lock the data. For example, for TMDS signals, the differential pairs of serial data must be strictly equal in length, but the skew between the data is relaxed to +/-20% of the clock cycle. However, in order to avoid unnecessary problems, generally speaking, serial signals such as TMDS and PCI-E must have equal lengths between channels, but the allowable deviation can be relatively large, such as 200ps or more.

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