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PCB Technical

PCB Technical - Topological structure of PCB trace and its applicable occasions

PCB Technical

PCB Technical - Topological structure of PCB trace and its applicable occasions

Topological structure of PCB trace and its applicable occasions

2021-09-25
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Author:Frank

Topological structure of PCB trace and its applicable occasions
Another way to solve the transmission line effect is to select the correct wiring path and terminal PCB topology. The topological structure of the wiring refers to the wiring sequence and wiring structure of a network cable. When using high-speed logic devices, unless the length of the trace branch is kept very short, signals with rapid edge changes will be distorted by the branch traces on the signal trunk trace. Under normal circumstances, the common topologies of PCB traces are:
(1) Point-to-point topology, single driver, single receiver. As long as proper impedance matching is performed on the driving end or the receiving end, better signal integrity can be obtained.
(2) The daisy chain topology uses the shortest interconnection transmission line to connect all the buffers, but each buffer can only be connected to the other two buffers through two transmission lines at most, starting from the main driver, and then connected through the transmission line Go to the buffer closest to the main drive, then find the closest unconnected buffer to the buffer, connect the two with a transmission line, and then look for the closest unconnected buffer again based on the buffer just added to the connection Connect the buffers, and so on, until all buffer connections are completed. After the connection is completed, starting from the main drive, all buffers are connected in a chain
(4) The star topology starts from the main driver. One signal driver drives multiple signal receivers, and when multiple signal receivers are required to receive signals at the same time, the receiving end load and wiring length of each branch should be kept as consistent as possible. Terminal resistors are generally required on the branches, and the resistance of the terminal resistors should match the characteristic impedance of the connection. In this way, good performance can be obtained even when the edge rate is very fast. The star topology structure can effectively avoid the asynchronous problem of the clock signal.
(5) The remote cluster shape is very similar to the star shape. The difference is that the last driver connected to the driver daisy chain is connected to a "T"-shaped node through a longer transmission line, and then all receivers are also Connected to this "T" node through a transmission line, all receivers are clustered together. The branch is close to the receiving end. In this topology, the length of the remote branch should also be limited so that the transmission delay on the branch is less than the rise or fall time of the signal.

pcb board

(6) Periodic load
The periodic load topology requires that the length of each branch is small enough so that the transmission delay on the branch is less than the rise or fall time of the signal. The structure of the main transmission line and all the branch sections can be regarded as a new transmission line. Its characteristic impedance is lower than that of the original main transmission line, and the transmission rate is also lower than the original. Therefore, it is necessary to perform impedance matching. Notice.

Which topological form the network connection should adopt, to a large extent, is determined by the requirements of the circuit, and then the convenience of layout and wiring.
(1) Point-to-point topology This topology is the simplest. It is easy to implement on layout and impedance control. Whether ordinary low-speed networks can adopt point-to-point topology depends entirely on the needs of the circuit; while for high-speed and ultra-high-speed interconnection, point-to-point interconnection is required in many cases, such as the interconnection of high-speed serial signals, to minimize The impact of impedance discontinuity; accurately timed clock signals are also not allowed to have bifurcations, because the impedance discontinuity caused by bifurcations will cause additional jitter.
(2) Daisy-chain topology Generally speaking, daisy-chain topology is often used for bus systems with multiple loads, and proper termination is performed at the farthest load.
Advantages of daisy chain routing:
It occupies a small wiring space and can be terminated by a single resistance matching; easy to control impedance, simple termination, short network wiring length, wiring is more convenient, as long as the difference in the receiving signal time of each receiver is within the allowable range Use daisy chain topology for wiring. For daisy chain wiring, the wiring starts from the driving end and reaches each receiving end in turn. If a series resistance is used to change the signal characteristics, the position of the series resistance should be close to the drive end. In the actual design, we make the branch length in the daisy chain wiring as short as possible. The safe length value should be:
In terms of controlling the high-order harmonic interference of the wiring, the effect is better.
Disadvantages of daisy chain routing:
The distribution rate is low, and it is not easy to achieve 100% distribution;
Different signal receiving ends, the signal reception is not synchronized., U" S1 x m% J* e
(3) Star topology. The star topology is also a commonly used multi-load wiring topology. The driver is located in the center of the star and is connected to multiple loads in a radial shape. The star topology can effectively avoid the unsynchronization of signals on multiple loads. The problem is that the signals received on the load can be completely synchronized. The problem with the star topology is that each branch needs to be terminated separately. There are many devices and the load of the driver is large. The driver must have the corresponding driving ability to use the star topology. If the driving ability is not enough, a buffer needs to be added. In order to reduce power consumption and relieve the load pressure of the driver, RC terminal termination can be used, but this termination method is more complicated and can only be used for clock signals. The star topology is generally used in clock networks or networks that require high signal synchronization. The common point is that each receiver is required to receive the signal from the driver at the same time. The wiring of the star topology is more difficult than the daisy chain topology. It takes up a lot of space. The actual star topology will have terminating transmission line branches, and there will be transmission line branches between the driver and the public node, which will degrade the signal, so the completion of the star topology generally requires pre-simulation and post-simulation to ensure signal integrity. The wiring starts from the driving end and reaches each receiving end in parallel, which can effectively avoid the problem of asynchronous clock signal.
(4) The remote cluster topology is actually an improvement of the star topology. It moves the branch node at the source end in the star topology to the remote end closest to the receiver, which meets the synchronization of the received signals on each receiver. The problem also solves the problem of complex impedance matching and heavy driver load, because the remote cluster topology only needs to match the terminal at the branch node. The remote cluster topology requires that the distance between each receiver and the branch point be as close as possible. The long branch line will seriously affect the quality of the signal. If the receiver chips cannot be placed together in space, then the remote cluster cannot be used.形topology. Similarly, pre-simulation and post-simulation are generally required to ensure signal integrity.
In short, when we are doing topology design, we can use it flexibly on the basis of the above classic topology. There is no fixed formula. A big principle is to ensure the signal quality. The weapon is to use SI software for topology analysis and simulation. In the actual PCB design process, for key signals, signal integrity analysis should be used to determine which topology to use