PCB News - How to choose the right PCB design tool

This article will explain the challenges faced by PCB design and what factors should be considered when evaluating a PCB design tool as a PCB designer.

The following are the factors that PCB designers must consider and will affect their decision:

1. Product function

A. The basic functions required by the cage cover include:

A. Interaction between schematic and PCB layout

B. Wiring functions such as automatic fan-out wiring, push-pull, etc., and wiring capabilities based on design rule constraints

C. Precise DRC checker

B. The ability to upgrade product functions when the company is engaged in a more complex design

A. HDI (High Density Interconnect) interface

B. Flexible design

C. Embedded passive components

D. Radio Frequency (RF) Design

E. Automatic script is born

F. Topological placement and routing

G. Manufacturability (DFF), Testability (DFT), Producibility (DFM), etc.

C. Additional products can perform analog simulation, digital simulation, analog-digital mixed signal simulation, high-speed signal simulation and RF simulation

D. Have a central component library that is easy to create and manage

2. A good partner who is technically in the leadership of the industry and has devoted more effort than other manufacturers, can help you design products with the greatest efficacy and leading technology in the shortest time

3. Price should be the most important consideration among the above factors. What needs more attention is the rate of return on investment!

There are many factors to consider in PCB evaluation. The type of development tools that designers are looking for depends on the complexity of the design work they are engaged in. Because the system is becoming more and more complex, the control of physical wiring and electrical component placement has developed to a very wide range, so that it is necessary to set constraint premises for the pivot path in the design process. However, too many design constraints have restricted the flexibility of design. Designers must have a good understanding of their design and its rules, so that they know when to use these rules.

It shows a typical integrated system design from front to back. It starts with the design definition (schematic diagram input), which is closely integrated with constraint codification. In constraint codification, the designer can define both physical constraints and electrical constraints. The electrical constraints will be analyzed before and after the layout of the network verification drive simulator. Take a closer look at the design definition, it is also linked to FPGA/PCB integration. The purpose of FPGA/PCB integration is to provide two-way integration, data management, and the ability to perform collaborative design between FPGA and PCB.

The same constraint rules for physical realization are entered during the layout phase as during the design definition. This reduces the probability of making mistakes from the file to the layout. Pin swapping, logic gate swapping, and even input-output interface group (IO_Bank) swapping all need to return to the design definition stage for updates, so the design of each link is synchronized.

During the evaluation period, the designer must ask himself: What scale is critical to them?

Let’s take a look at some trends that force designers to review their existing development tool features and start ordering some new features:

1.RF design

For RF design, the RF circuit should be directly designed as a system schematic diagram and system board layout, and not used in a separate environment for subsequent conversion. All the simulation, tuning and optimization capabilities of the RF simulation environment are still necessary, but the simulation environment can accept more primitive data than the "real" design. Therefore, the differences between the data models and the resulting design conversion issues will disappear. First, designers can directly interact between system design and RF simulation; second, if designers perform a large-scale or reasonably complex RF design, they may want to distribute circuit simulation tasks to multiple computing platforms running in parallel, or They want to send each circuit in a design composed of multiple modules to their respective simulators, thereby reducing simulation time.

2.HDI

"The increase in the complexity of semiconductors and the total amount of logic gates has required integrated circuits to have more pins and finer pin pitches. It is very common nowadays to design more than 2000 pins on a BGA device with a pin pitch of 1mm, let alone arrange 296 pins on a device with a pin pitch of 0.65mm. The need for faster and faster rise times and signal integrity (SI) requires a greater number of power and ground pins, so it needs to occupy more layers in the multi-layer board, thus driving the high level of microvias. The need for HDI technology.

HDI is an interconnection technology being developed in response to the above-mentioned needs. Micro vias and ultra-thin dielectrics, finer traces and smaller line spacing are the main features of HDI technology.

3. Rigid flexible PCB

In order to design a rigid flexible PCB, all factors that affect the assembly process must be considered. The designer cannot simply design a rigid flexible PCB like a rigid PCB, just like the rigid flexible PCB is nothing more than another rigid PCB. They must manage the bending area of the design to ensure that the design points will not cause the conductor to break and peel off due to the stress of the bending surface. There are still many mechanical factors to consider, such as minimum bending radius, dielectric thickness and type, metal sheet weight, copper plating, overall circuit thickness, number of layers, and number of bending sections.

Understand rigid flexible design and decide whether your product allows you to create a rigid flexible design.

4. Package

The increasing functional complexity of modern products requires a corresponding increase in the number of passive components, which is mainly reflected in the increase in the number of decoupling capacitors and terminal matching resistors in low-power, high-frequency applications. Although the packaging of passive surface mount devices has shrunk considerably after several years, the results are still the same when trying to achieve the maximum density. The technology of printed components makes the transition from multi-chip components (MCM) and hybrid components to SiP and PCBs that can be directly used as embedded passive components today. In the process of transformation, the latest assembly technology was adopted. For example, the inclusion of a resistive material layer in a layered structure and the use of series termination resistors directly under the uBGA package greatly improve the performance of the circuit. Now, embedded passive components can be designed with high precision, thus eliminating the need for additional processing steps for laser cleaning of welds. The wireless components are also moving in the direction of improving integration directly in the substrate.

5. Signal integrity planning

In recent years, new technologies related to parallel bus structure and differential pair structure for serial-parallel conversion or serial interconnection have been continuously improved. Types of typical design problems encountered in a parallel bus and serial-to-parallel conversion design. The limitation of parallel bus design lies in system timing changes, such as clock skew and propagation delay. Because of the clock skew over the entire bus width, the design for timing constraints is still difficult. Increasing the clock rate will only make the problem worse.

On the other hand, the differential pair structure uses an exchangeable point-to-point connection at the hardware level to realize serial communication. Usually, it transfers data through a one-way serial "channel", which can be superimposed into 1-, 2-, 4-, 8-, 16-, and 32-width configurations. Each channel carries one byte of data, so the bus can handle data widths from 8 bytes to 256 bytes, and data integrity can be maintained by using some forms of error detection techniques. However, because of the high data rate, other design issues arise. Clock recovery at high frequencies becomes the burden of the system. Because the clock needs to quickly lock the input data stream, and in order to improve the anti-shake performance of the circuit, it is necessary to reduce the jitter from cycle to cycle. Power supply noise also poses additional problems for designers. This type of noise increases the possibility of severe jitter, which will make eye opening more difficult. Another challenge is to reduce common mode noise and solve problems caused by loss effects from IC packages, PCB boards, cables, and connectors.

It seems that it is easy to get a PCB board tool that can handle the layout; but it is crucial to get a tool that not only satisfies the layout but also solves your urgent needs.