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The wiring of the PCI card is more exquisite, which is determined by the characteristics of the PCI signal.
In conventional high-frequency digital circuit design, we always strive to avoid signal reflection, overshoot, ringing, and non-monotonicity caused by impedance mismatch. However, PCI signals use the principle of signal reflection to transmit physical signals. In order to make reasonable use of signal reflection while trying to avoid side effects such as large overshoot, ringing, and non-monotonicity, PCI-SIG has made some provisions for PCB physical implementation in the PCI specification.
PCI-SIG recommends that PCI cards use a four-layer PCB board. The signal distribution of the PCI connector specified by PCI-SIG is also optimized for the convenience of four-layer board wiring. PCI-SIG has also made a recommended schematic diagram for the pin distribution of PCI controllers. In fact, PCI controller manufacturers such as AMCC, PLX, and OXFORD have also implemented this recommendation. Under this recommended pin distribution, two layers are used. The PCB board is actually very convenient for wiring, but if the PCI card system hardware is very complex and requires multiple power split levels, it is better to have a multi-layer PCB.
Any PCI signal on the PCI card can only be connected to one load (including and cannot be connected to a pull-up resistor). Except for CLK, RST, INTA#~INTD#, JTAG these pins, all pins from the contact point of the golden finger and the card socket to the load end shall not be larger than 1.5 inches; the length of the CLK signal is 2.5 +-0.1 inch, this length It's a bit long, so in many cases it needs to be routed around to meet the length requirement. This is why you often see the serpentine trace of CLK on the PCI card; there are no special regulations for the remaining pins. When multi-layer PCB, signal traces should not cross different power levels (at least, the layer with split power level should be on the other side of the PCB), which is why we often see all the golden fingers on the A side of the PCI card come up The reason why the signal often goes to the B side (component side) through a hole.
The characteristic impedance of each PCI signal is 60-100 ohms, and the load capacitance must not exceed 10pf. The IO Pad of the IC should be able to withstand -3.5V undershoot and +7.1V signal overshoot. For PCI controller manufacturers such as AMCC, PLX, and OXFORD, their controller ICs all meet these regulations, users do not need to consider, but if you use CPLD/FPGA to implement PCI controllers, you must consider whether the model used meets these regulations Generally, CPLD/FPGA manufacturers such as Altera and Xilinx will clearly state in their data manuals whether the CPLD/FPGA is compatible with PCI signal specifications.
Okay, the wiring of an ordinary 32-bit 33MHz PCI card is relatively simple, and it is enough to meet the length requirements. In fact, if you do not strictly follow the wiring requirements, there will generally be no problems, but depending on the motherboard chipset, once the signal compatibility problem occurs, the hardware debugging of the PCI card will be the most painful experience in the PCB design.
