PCB News - Questions and answers about high-speed PCB design experts

1. How to realize the differential wiring of high-speed clock signals? How to solve the signal integrity problem in high-speed design? How is the differential wiring method realized? How to implement differential wiring for a clock signal line with only one output terminal?

Expert answers:

Signal integrity is basically a problem of impedance matching. The factors that affect impedance matching include the structure and output impedance of the signal source, the characteristic impedance of the trace, the characteristics of the load end, and the topology of the trace. The solution is to rely on the topology of termination and adjustment of the wiring.

There are two points to pay attention to in the layout of the differential pair. One is that the length of the two wires should be as long as possible, and the other is that the distance between the two wires (this distance is determined by the differential impedance) has to be kept constant, that is, to keep parallel. There are two parallel ways, one is that the two wires run on the same side-by-side, and the other is that the two wires run on two adjacent layers above and below (over-under). Generally, the former has more side-by-side implementations.

To use differential wiring, it makes sense that both the signal source and the receiving end are differential signals. Therefore, it is impossible to use differential wiring for a clock signal with only one output terminal.

2. About high-speed differential signal wiring. When high-speed differential signal line pairs are routed in parallel on the PCB board, in the case of impedance matching, due to the mutual coupling of the two wires, it will bring many benefits. However, there are opinions that this will increase the attenuation of the signal and affect the transmission distance. Is it so and why? I saw on the evaluation boards of some large companies that some of the high-speed wiring was as close and parallel as possible, while some deliberately caused the distance between the two wires to be far and near. I don't know which one is better. My signal is above 1GHz and the impedance is 50 ohms.

When using software to calculate, is the differential pair also calculated with 50 ohms? Or is it calculated in 100 ohms? Can a matching resistor be added between the differential line pairs at the receiving end? Thanks!

Expert answers:

One reason for the attenuation of high-frequency signal energy is the conductor loss (conductor loss), including the skin effect, and the other is the dielectric loss of the dielectric substance. These two factors can be seen in the degree of their influence on signal attenuation when the electromagnetic theory analyzes the transmission line effect. The coupling of the differential line will affect their characteristic impedance and become smaller. According to the voltage divider principle (voltage divider), this will make the voltage sent by the signal source to the line smaller. As for the theoretical analysis of signal attenuation due to coupling, I have not read it, so I cannot comment on it.

The wiring of the differential pair should be appropriately close and parallel. The so-called appropriate proximity is because the distance will affect the value of differential impedance, which is an important parameter for designing differential pairs. The need for parallelism is also to maintain the consistency of the differential impedance. If the two lines are suddenly far and near, the differential impedance will be inconsistent, which will affect the signal integrity and timing delay.

The calculation of the differential impedance is 2 (Z11-Z12), where Z11 is the characteristic impedance of the trace itself, and Z12 is the impedance generated by the coupling between the two differential lines, which is related to the line distance. Therefore, when the differential impedance is designed to be 100 ohms, the characteristic impedance of the trace itself must be slightly greater than 50 ohms. As for how big it is, it can be calculated with simulation software. The matching resistance between the differential line pairs at the receiving end is usually added, and its value should be equal to the value of the differential impedance. This way the signal quality will be better.

3. How to deal with some theoretical conflicts in actual wiring. In actual wiring, many theories conflict with each other; for example:

1. Deal with the connection of multiple analog/digital grounds: theoretically they should be isolated from each other, but in actual miniaturization and high-density wiring, due to space limitations or absolute isolation, small-signal analog ground traces will be too long. It is difficult to achieve theoretical connection. My approach is to divide the ground of the analog/digital function module into a complete island, and the analog/digital ground of the function module is connected to this island. Then connect the island to the "big" ground through the trench. I wonder if this approach is correct?

2. In theory, the connection between the crystal oscillator and the CPU should be as short as possible. Due to the structural layout, the connection between the crystal oscillator and the CPU is relatively long and thin, so it is interfered and the work is unstable. How to solve this problem from the wiring? There are many other issues like this, especially EMC and EMI issues are considered in high-speed PCB wiring. There are many conflicts, which is a headache. How can I resolve these conflicts? Thanks a lot!

Expert answers:

A Basically, it is right to divide and isolate the analog/digital ground. It should be noted that the signal trace should not cross the divided place (moat) as much as possible, and the return current path of the power supply and signal should not be too large.

B crystal oscillator is an analog positive feedback oscillation circuit. To have a stable oscillation signal, it must meet the loop gain and phase specifications. The oscillation specifications of this analog signal are easily disturbed. Even if ground guard traces are added, it may not be able to completely isolate the interference. And if it is too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. Therefore, the distance between the crystal oscillator and the chip must be as close as possible.

C It is true that there are many conflicts between high-speed wiring and EMI requirements. But the basic principle is that the resistance and capacitance or ferrite bead added by EMI cannot cause some electrical characteristics of the signal to fail to meet the specifications. Therefore, it is best to use the skills of arranging traces and PCB stacking to solve or reduce EMI problems, such as high-speed signals going to the inner layer. Finally, the resistance capacitor or ferrite bead method is used to reduce the damage to the signal.

4. The problem of anti-interference in the analog and digital part. There are often A/Ds in some systems. Question: To improve anti-interference, apart from the separation of analog ground and digital ground, only connect at one point of the power supply, and thicken the ground and power lines. Hope the experts will give some good opinions and suggestions!

Expert answers:

In addition to the ground isolation, also pay attention to the power supply of the analog circuit part. If the power supply is shared with the digital circuit, it is better to add a filter circuit. In addition, the digital signal and the analog signal should not be interlaced, especially not across the divided ground (moat).

5. Automatic wiring of high-speed signals. In order to maximize the quality of high-speed signals, we are accustomed to manual wiring, but the efficiency is too low. The use of automatic routers can not monitor the winding method of key signals, the number of vias, and the location. Manual routing of key signals and then automatic routing will reduce the layout rate of automatic routing, and the adjustment of automatic routing results means more routing workload, how to balance the above contradictions, and use excellent routers to help complete the routing of high-speed signals?

Expert answers:

Most of the automatic routers of strong wiring software now have set constraints to control the winding method and the number of vias. The winding engine capabilities and constraint setting items of various EDA companies sometimes differ greatly. For example, whether there are enough constraints to control the way of serpentine winding, whether it is possible to control the trace spacing of the differential pair, etc. This will affect whether the routing method of the automatic routing can meet the designer's idea. In addition, the difficulty of manually adjusting the wiring is also absolutely related to the ability of the winding engine. For example, the pushing ability of the trace, the pushing ability of the via, and even the pushing ability of the trace to the copper coating and so on. Therefore, choosing a router with strong winding engine capability is the solution.

6Are there any specifications for the design of test coupon. Can you refer to it? How to design the test coupon according to the actual situation of the board? Are there any issues that need attention? Thanks!

Expert answers:

The test coupon is used to measure whether the characteristic impedance of the produced PCB board meets the design requirements with TDR (Time Domain Reflectometer). Generally, the impedance to be controlled has two cases: a single line and a differential pair. Therefore, the line width and line spacing on the test coupon (when there is a differential pair) should be the same as the line to be controlled. The most important thing is the location of the grounding point during measurement. In order to reduce the inductance of the ground lead, the grounding place of the TDR probe is usually very close to the probe tip. Therefore, the distance and method between the signal measurement point and the ground point on the test coupon Must match the probe used.

7. Regarding the problem of copper-clad grounding in the blank area of the signal layer in high-speed PCB design. In high-speed PCB design, the blank area of the signal layer can be copper-clad, so is the copper of multiple signal layers grounded well, or half-grounded and half-grounded How about connecting to the power supply?

Expert answers:

Generally, the copper plating in the blank area is mostly grounded. Just pay attention to the distance between the copper and the signal line when applying copper next to the high-speed signal line, because the applied copper will reduce the characteristic impedance of the trace a little. Also be careful not to affect the characteristic impedance of other layers, for example in the structure of the dual stripline.

8. Characteristic impedance. Thank you for answering my last question. Last time you said that the power plane and the ground plane are basically metal planes, so there is a shielding effect on the electric field and magnetic field. Can I use the microstrip line model to calculate the characteristic impedance of the signal line on the power plane? Can the signal between time be calculated using the stripline model?

Expert answers:

Yes, when calculating the characteristic impedance, both the power plane and the ground plane must be regarded as reference planes. For example, a four-layer board: top layer-power layer-ground layer-bottom layer. At this time, the characteristic impedance model of the top layer is a microstrip line model with the power plane as the reference plane.

9. The problem of matching high-speed signal lines. In the layout of high-speed boards (such as p4 motherboards), why are high-speed signal lines (such as cpu data and address signal lines) required to match? What hidden dangers will there be if they do not match? What factors determine the matching length range (that is, the time delay difference of the signal line), and how to calculate it?

Expert answers:

The main reason for the characteristic impedance matching of the trace is to avoid the reflection caused by the high-speed transmission line effect from affecting the signal integrity and the flight time. In other words, if it does not match, the signal will be reflected to affect its quality.

The length range of all traces is set according to the timing requirements. There are many factors that affect the signal delay time, and the trace length is only one of them. P4 requires that the length of certain signal lines should be within a certain range. It is the timing margin calculated according to the transmission mode (common clock or source synchronous) used by the signal, and a part of the allowable error of the trace length is allocated. As for the calculation of the time sequence of the above two modes, it is not convenient to describe in detail here due to time and space limitations.