PCB News - When does PCB wiring need impedance matching

Impedance matching refers to the requirement that the load impedance should be equal to the characteristic impedance of the transmission line during energy transmission, so that the transmission does not generate reflection, indicating that all the energy is absorbed by the load. Otherwise, energy is lost in transmission. In high-speed PCB design, impedance matching is related to signal quality.

1. When does PCB wiring need impedance matching?

It is generally believed that if the signal's rise/fall time (10% ~ 90%) is less than 6 times wire delay, it is a high-speed signal, and attention must be paid to the problem of impedance matching. Generally, the delay of a wire is 150ps/inch.

2. Characteristic impedance

As a signal travels along a transmission line, the signal will always see exactly the same transient impedance if the signal has the same signal velocity throughout the line and the same capacitance per unit length. Since the impedance remains constant throughout the transmission line, we give a specific name for this characteristic or characteristic of a particular transmission line, called the characteristic impedance of the transmission line. The characteristic impedance is the value of the instantaneous impedance that a signal sees as it travels along a transmission line. The characteristic impedance is related to the PCB conductor layer, the PCB material (dielectric constant), the wiring width, the distance between the conductor and the plane and other factors, and has nothing to do with the wiring length. The characteristic impedance can be calculated using software. In high-speed PCB wiring, the wiring impedance of digital signal is generally designed to be 50 ohms, which is an approximate number. It is generally stipulated that the coaxial cable base band is 50 ohms, the frequency band is 75 ohms, and the twisted pair (difference) is 100 ohms. Learn PCB find Fan Yi education high quality PCB training

3. Common impedance matching modes

1) Series terminal matching Under the condition that the source impedance of the signal is lower than the characteristic impedance of the transmission line, a resistance R is connected in series between the source end of the signal and the transmission line, so that the output impedance of the source end matches the characteristic impedance of the transmission line and inhibits the signal reflected back from the load end to reflect again. Matching resistance selection principle: The sum of matching resistance value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. Common CMOS and TTL drivers whose output impedance varies with the signal level. Therefore, for TTL or CMOS circuits, it is impossible to have a very correct matching resistor, only compromise. The chain topology of the signal network is not suitable for series terminal matching, all the load must be connected to the end of the transmission line. Series matching is a common terminal matching method. It has the advantage of low power consumption, no additional DC load on the driver, no additional impedance between the signal and the ground, and only one resistive element is required. Common applications: impedance matching of CMOS and TTL circuits. USB signals are also sampled this way to do impedance matching.

2) Parallel terminal matching When the source impedance of signal is very small, the input impedance of the load end is matched with the characteristic impedance of the transmission line by increasing the parallel resistance, so as to eliminate the reflection of the load end. The realization form is divided into two forms of single resistance and double resistance. Matching resistance selection principle: in the case of high chip input impedance, for the form of single resistance, the parallel resistance value at the load end must be close to or equal to the characteristic impedance of the transmission line; For the double resistance form, each parallel resistance value is twice the characteristic impedance of the transmission line. The advantage of parallel terminal matching is simple and easy, but the obvious disadvantage is that it will bring DC power consumption: dc power consumption of single resistance mode is closely related to the duty ratio of signal; Dual-resistance mode has dc power consumption regardless of whether the signal is at high or low level, but the current is half less than single-resistance mode.

4. Common applications: high-speed signals are widely used

1) DDR, DDR2 and other SSTL drivers. In the form of a single resistor, parallel to VTT (generally half of the IOVDD). The parallel matching resistor of DDR2 data signal is built in the chip.

2) High-speed serial data interface such as TMDS. In the form of single resistance, the receiving device is connected to the IOVDD in parallel, and the single-end impedance is 50 ohms (100 ohms between difference pairs).