PCB News - Wiring design based on electromagnetic compatibility technology

Multilayer circuit board wiring PCB designmethod based on electromagnetic compatibility technology
Electromagnetic Compatibility (Electro-Magnetic Compatibility, EMC for short) is an emerging comprehensive discipline, which mainly studies electromagnetic interference and anti-interference issues. Electromagnetic compatibility means that the electronic equipment or system does not reduce the performance index due to electromagnetic interference under the specified electromagnetic environment level, and the electromagnetic radiation generated by them is not greater than the limited limit level, and does not affect the normal operation of other systems. And achieve the goal of non-interference between equipment and equipment, system and system, and work together reliably. Electromagnetic interference (EMI) is caused by electromagnetic interference sources transmitting energy to sensitive systems through coupling paths. It includes three basic forms: conduction by wires and public ground wires, and through space radiation or near-field coupling. Practice has proved that even if the circuit schematic is designed correctly and the printed circuit board is not properly designed, it will have an adverse effect on the reliability of electronic equipment. Therefore, ensuring the electromagnetic compatibility of the printed circuit board is the key to the entire system design. This article mainly discusses electromagnetic compatibility Technology and its application in multi-layer printed circuit board (Printed Circuit Board, PCB for short) design. The article is quoted from Shenzhen Honglijie Electronics!

PCB board is the support of circuit components and devices in electronic products. It provides electrical connections between circuit components and devices and is the most basic component of various electronic equipment. Nowadays, large-scale and very large-scale integrated circuits have been widely used in electronic equipment, and the mounting density of components on printed circuit boards is getting higher and higher, and the signal transmission speed is getting faster and faster. EMC problems have become more and more prominent. PCB has single-sided board (single-layer board), double-sided board (double-layer board) and multi-layer board. Single and double panels are generally used for low- and medium-density wiring circuits and low-integration circuits, and multi-layer boards use high-density wiring and high-integration circuits. From the perspective of electromagnetic compatibility, single-sided and double-sided boards are not suitable for high-speed circuits. Single-sided and double-sided wiring can no longer meet the requirements of high-performance circuits. The development of multilayer wiring circuits provides a possibility to solve the above problems. The application becomes more and more extensive.

1 Characteristics of multilayer wiring

The PCB is composed of organic and inorganic dielectric materials with a multi-layer structure. The connections between the layers are realized through via holes. The via holes are plated or filled with metal materials to realize electrical signal conduction between the layers. The reason why multi-layer wiring has been widely used has the following characteristics:

(1) A dedicated power layer and grounding layer are provided inside the multilayer board. The power layer can be used as a noise loop to reduce interference; at the same time, the power layer also provides a loop for all signals in the system to eliminate common impedance coupling interference. Reduce the impedance of the power supply line, thereby reducing the common impedance interference.

(2) The multi-layer board uses a special grounding layer, and there are special grounding wires for all signal lines. The characteristics of the signal line: stable impedance and easy matching, reducing the waveform distortion caused by reflection; at the same time, the use of a special ground layer increases the distributed capacitance between the signal line and the ground line and reduces crosstalk.

2 Laminated design of printed circuit board

2.1 PCB wiring rules

The electromagnetic compatibility analysis of multilayer circuit boards can be based on Kirchhoff's law and Faraday's law of electromagnetic induction. According to Kirchhoff's law, any time-domain signal from source to load must have a path with the lowest impedance.

PCBs with multiple layers are often used in high-speed, high-performance systems, where multiple layers are used for direct current (DC) power or ground reference planes. These planes are usually solid planes without any division, because there are enough layers for power or ground, so there is no need to put different DC voltages on the same layer. This layer will be used as a current return path for signals on the transmission lines adjacent to them. Constructing low-impedance current return paths is the most important EMC goal of these plane layers.

The signal layers are distributed between the physical reference plane layers, and they can be symmetrical striplines and asymmetrical striplines. Take a 12-layer board as an example to illustrate the structure and layout of the multilayer board. The layered structure is T-P-S-P-S-P-S-P-S-S-P-B, "T" is the top layer, "P" is the reference plane layer, and "S" is the signal layer. "B" is the bottom layer. From the top layer to the bottom layer are the first layer, the second layer, and the twelfth layer. The top and bottom layers are used as pads for components. Signals should not be transmitted too long between the top and bottom layers in order to reduce direct radiation from the traces. Incompatible signal lines should be isolated from each other. The purpose of this is to avoid coupling interference between each other. High-frequency and low-frequency, high-current and small-current, digital and analog signal lines are incompatible. In the component layout, incompatible components should be placed in different positions on the printed board. The layout of the signal lines is still necessary. Be careful to isolate them. Pay attention to the following 3 issues when designing:

(1) Determine which reference plane layer will contain multiple power supply regions for different DC voltages. Assuming that the 11th layer has multiple DC voltages, it means that the designer must keep the high-speed signal as far away as possible from the 10th layer and the bottom layer, because the return current cannot flow through the reference plane above the 10th layer, and stitching capacitors are required. Layers 5, 7 and 9 are signal layers for high-speed signals. The traces of important signals should be laid out in one direction as much as possible to optimize the number of possible trace channels on the layer. The signal traces distributed on different layers should be perpendicular to each other, which can reduce the coupling interference of electric and magnetic fields between the lines. The 3rd and 7th layers can be set as "east-west" traces, and the 5th and 9th layers are set Route the lines for "North and South". The layer of the routing cloth depends on the direction it reaches the destination.

(2) Layer changes during high-speed signal routing, and which different layers are used for an independent routing, to ensure that the return current flows from a reference plane to a new reference plane as needed. This is to reduce the signal loop area and reduce the loop's differential mode current radiation and common mode current radiation. Loop radiation is proportional to current intensity and loop area. In fact, the best design does not require the return current to change the reference plane, but simply changes from one side of the reference plane to the other. For example, a combination of signal layers can be used as signal layer pairs: layer 3 and layer 5, layer 5 and layer 7, layer 7 and layer 9, which allows an east-west direction and a north-south direction to form a wiring combination. But the combination of layer 3 and layer 9 should not be used, because this requires the return current to flow from layer 4 to layer 8. Although a decoupling capacitor can be placed near the via, at high frequencies, the capacitor is useless due to the presence of lead and via inductance. And this kind of wiring will increase the area of the signal loop, which is unfavorable to reduce current radiation.

(3) Select the DC voltage for the reference plane layer. In this example, due to the high speed of signal processing inside the processor, there is a lot of noise on the power/ground reference pin. Therefore, it is very important to use decoupling capacitors to provide the same DC voltage to the processor, and to use decoupling capacitors as efficiently as possible. The best way to reduce the inductance of these components is to connect the traces as short and wide as possible, and to make the vias as short and thick as possible.

If the second layer is allocated as "ground" and the fourth layer is allocated as the processor's power supply, the vias should be as short as possible from the top layer where the processor and decoupling capacitors are placed. The remaining part of the space that extends to the bottom layer of the board does not contain any important currents, and the short distance does not have an antenna effect. Table 1 lists the reference configuration of the stacked design layout.

2.2 20-H rule and 3-W rule

In the electromagnetic compatibility design of the multilayer PCB board, there are two basic principles to determine the distance between the power layer of the multilayer board and the edge and to solve the distance between the printed strips: 20-H rule and 3-W rule.

20-H principle: Due to the connection between the magnetic flux, RF current usually exists at the edge of the power plane. This inter-layer coupling is called edge effect. When high-speed digital logic and clock signals are used, the power planes will interact with each other. Couple the RF current, as shown in Figure 1. In order to reduce this effect, the physical size of the power plane should be at least 20H smaller than the physical size closest to the ground plane (H is the distance between the power plane and the ground plane). The edge effect of the power supply usually occurs at about 10H, 20H When about 10% of the magnetic flux is blocked, if you want to achieve 98% of the magnetic flux is blocked, you need a 100% boundary value, as shown in Figure 1. The 20-H rule determines the physical distance between the power plane and the nearest ground plane. This distance includes copper thickness, pre-filling, and insulating separation layer. Using 20-H can increase the resonant frequency of the PCB itself.
3-W rule: When the distance between two printed lines is small, electromagnetic crosstalk will occur between the two lines, which will cause the related circuit to malfunction. In order to avoid this interference, keep any line spacing not less than 3 times the printing Line width, that is, not less than 3W (W is the printed line width). The width of the printed line depends on the requirements of line impedance. Too wide will affect the wiring density, and too narrow will affect the integrity and strength of the signal transmitted to the terminal. The wiring of clock circuits, differential pairs, and I/O ports are all basic application objects of the 3-W principle. The 3-W principle only represents the boundary of the electromagnetic flux line at which crosstalk energy attenuates by 70%. If the requirements are higher, such as the electromagnetic flux boundary line at which the crosstalk energy attenuation is attenuated by 98%, the interval of 10W must be adopted.

2.3 the arrangement of the ground wire

First of all, we must establish the concept of distributed parameters. When the frequency is higher than a certain frequency, any metal wire must be regarded as a device composed of resistance and inductance. Therefore, the grounding lead has a certain impedance and constitutes an electrical loop. Whether it is single-point grounding or multi-point grounding, it must form a low-impedance loop to enter the real ground or rack. A typical printed line with a length of 25mm will show approximately 15-20nH inductance. Together with the presence of distributed capacitance, a resonant circuit will be formed between the ground plate and the equipment rack. Secondly, when the ground current flows through the ground line, it will produce transmission line effect and antenna effect. When the length of the line is 1/4 wavelength, it shows a high impedance, the grounding wire is actually an open circuit, and the grounding wire becomes an antenna radiating outward instead. Finally, the grounding plate is filled with eddy currents formed by high-frequency currents and disturbances. Therefore, many loops are formed between grounding points. The diameter of these loops (or distance between grounding points) should be less than 1/20 of the wavelength of the highest frequency. Choosing the right device is an important factor for design success. Especially when choosing a logic device, try to choose a logic device with a rise time longer than 5ns. Never choose a logic device with a timing faster than the circuit requires.

2.4 The arrangement of the power cord

For multi-layer boards, the power supply layer-ground layer structure is used for power supply. The characteristic impedance of this structure is much smaller than that of the track pair, which can be less than 1Ω. This structure has a certain capacitance, and there is no need to add high-frequency decoupling capacitors next to each integrated chip. Even if the capacity of the layer capacitor is not enough, when an external decoupling capacitor is needed, it should not be added next to the integrated chip, but can be added anywhere on the printed board. The power pin and ground pin of the integrated chip can be directly connected to the power layer and ground layer through metallized through holes, so the power supply loop is always the smallest. Due to the principle of "current always taking the path of least impedance", the high-frequency return flow on the ground always runs close to the track, unless there is a barrier to block the ground, so the signal loop is always the smallest. It can be seen that the power layer-stratum structure has the advantages of simple and flexible layout and good electromagnetic compatibility compared with the power supply of the trajectory.