PCB Technical - The clock stabilization design of pcb proofing high-speed A/D converter

In recent years, foreign research on high-speed A/D converters has been the most active, and some improved structures have appeared in the basic Flash structure [2], such as subranging circuit structures (such as half-flash structure, Pipelined, Multistage structure, Multistep structure). In fact, they are a circuit structure composed of multiple Flash circuit structures and other functional circuits in different forms. This structure can make up for the shortcomings of the basic Flash circuit structure and is a high-speed, high-resolution A/D converter. This kind of structure is gradually replacing the long-standing SAR and integral structure, and there is also a type of bit-per-stage circuit structure. Further improvement on the basis of it, you will get a A circuit structure called Folding (also called Mag Amps structure) This is a Gray code serial output structure. These PCB circuit design techniques are the development of high-speed, high-resolution, and high-performance A/D converters. Played a positive role in promoting.

In addition, in the circuit design technology of high-resolution A/D converters, the Σ-Δ circuit structure is currently a very popular circuit design technology. This circuit structure is not only used in high-resolution low-speed or medium-speed A/D converters. Will gradually replace the SAR and integral circuit structure, and this structure combined with the pipeline structure, is expected to achieve higher resolution, and higher speed A/D converter.
PCB proofing clock duty cycle stabilization circuit
With the continuous expansion and performance improvement of electronic systems in weapons and equipment in the new era, the complexity of electronic systems is also increasing. In order to ensure the capabilities and performance of data sampling, control feedback, and digital processing of electronic systems, modern military electronic systems The requirements for A/D converters are also getting higher and higher, especially for military data communication systems and data acquisition systems. The demand for high-speed and high-resolution A/D converters is increasing. The clock duty cycle stabilization circuit is used as a high-speed, The core unit of the high-precision A/D converter plays a vital role in the performance of the converter’s signal-to-noise ratio (SNR) and effective bit (ENOB). Therefore, it is necessary to ensure the high-speed, high-precision A/D converter For performance, it is necessary to ensure that the sampling and encoding clock has a suitable duty cycle and small jitter. Therefore, it is very necessary to carry out research on the clock duty cycle stabilization circuit.
Since the clock duty cycle stabilization circuit is the core unit of high-speed, high-precision A/D converters, and there are almost no products with separate clock duty cycle stabilization circuits, it is only reported in high-speed, high-precision A/D converters. Compared with the products of other companies, ADI's products can improve the sampling performance mainly due to the improvement of the DCS (duty cycle stabilizer) circuit. The DCS circuit is responsible for reducing the jitter of the clock signal, and the sampling timing depends on the clock. Signals, the previous DCS circuits of various companies can only control the jitter to about 0.25ps, while the new high-performance products AD9446 and LTC2208 can reduce the jitter to about 50fs. Generally, reducing the jitter can improve the SNR, thereby increasing the effective resolution ( ENOB: effective number of bits), and can achieve a sampling rate of more than 100Msps while reaching a 16-bit quantization number. If the sampling rate is increased without controlling the jitter, the ENOB will be reduced and the desired resolution cannot be obtained. It is impossible to increase the number of quantization bits. With the development of high-performance A/D converters, DCS circuits can develop in the direction of higher speed, less jitter and stability. Table 1 lists the clock duty in foreign A/D converters. The main technical and parameter indicators of the stable circuit.
In fact, so far, AD's 60fs jitter has been the smallest. Now the aperture jitter is generally controlled at about 1 ps, and jitter higher than this number or even tens of ps is actually of little significance.
Realization method of PCB proofing clock stabilization circuit
From the current research situation at home and abroad, the clock circuit used to stabilize the high-speed ADC is mainly a phase-locked loop (Phase-locked loop, PLL). The phase-locked system is essentially a closed-loop phase control system. Simply put, it is a circuit that can synchronize the output signal with the input signal in terms of frequency and phase, that is, after the system enters the locked state (or synchronized state), The phase difference between the output signal of the oscillator and the input signal is zero or remains constant. Because the phase-locked loop has many excellent characteristics, it can be widely used in high-performance processor clock generation and distribution, system frequency synthesis and conversion, and automatic Frequency tuning tracking, bit synchronization extraction in digital communication, phase lock, phase lock frequency multiplication and frequency division, etc.
This article proposes a delay-locked loop DLL (Delay-locked loop DLL) design. In fact, the PLL mainly uses the phase detector and filter to monitor the feedback clock signal and the input clock signal, and then use the generated voltage difference Control the voltage-controlled oscillator to generate a signal similar to the input clock, and finally achieve the purpose of frequency locking. The function of the DLL is to insert a delay pulse between the input clock and the feedback clock until the rising edges of the two clocks are aligned, and When synchronization is achieved, when the input clock pulse edge and the feedback pulse edge are aligned, the on-chip delay phase-locked loop DLL can all be locked. After the clock is locked, the circuit is no longer adjusted and there is no difference between the two clocks. In this way, the on-chip delay phase-locked loop uses the DLL output clock to compensate for the time delay caused by the clock distribution network, thereby effectively improving the clock source and load. Time delay between. First of all, the delay line is less noisy than the oscillator. This is because the damaged zero-crossing point in the waveform disappears at the end of the delay line, and it recirculates in the oscillator circuit, which generates more Secondly, the delay time is rapidly changed within the control voltage change in the DLL, that is, the transfer function is simply equal to the gain KBCDL of the VCDL. In short, the oscillator used in the PLL has instability and phase offset Accumulation, when the compensation clock separately causes time delay in the network, it tends to reduce the performance of the PLL. Therefore, the stability and stable speed of the DLL are better than the PLL.

The PCB board test system will have a new PCB design idea, adopting the USB bus-based automatic test system and virtual instrument design ideas, giving full play to the role of the computer, and replacing the traditional instrument idea with a computer as much as possible, thereby reducing The volume of the instrument itself reduces the development cost, thereby improving the efficiency of development.
After D/A conversion, the analog excitation signal required for the test is applied to the test system, and then the test circuit is sent to the switch matrix through the test bus. The switch matrix is connected to the switch matrix and controlled by the microprocessor to turn on and off. The test PCB board is fixed on the needle bed, the excitation signal is applied to the corresponding position of the printed circuit board, the response is measured by the test circuit, and the collected analog quantity is sent to the core control. After A/D conversion, the corresponding The digital quantity is fed back by the software on the PCB machine and processed by the PCB machine to determine whether the PCB board is qualified.