PCB Technical - Do you know any tips in PCB design?

1. In PCB design, using protel 99se software design, the processor is 89C51, there is a 40KHZ ultrasonic signal and 800hz audio signal in the crystal oscillator 12MHZ system, how to design the PCB at this time to provide high anti-interference ability?

For single-chip microcomputers such as 89C51, how much signal can affect the normal operation of 89C51? In addition to increasing the distance between the two, are there other techniques to improve the system's anti-interference ability?

PCB design provides high anti-interference ability. Of course, it is necessary to minimize the signal edge rate of the interference source signal. The specific high frequency signal depends on the level of the interference signal and how long the PCB wiring is. In addition to widening the gap, the reflection and overshoot of interference signals can be solved by matching or topology, which can also effectively reduce signal interference.

2. If you want to reduce the board area as much as possible, but plan to paste the front and back like a memory stick, can you?

Positive and negative PCB design, as long as your welding process is no problem, of course.

3. Do you need to pay attention to the distribution and wiring of power supply in PCB wiring as well as grounding. What kind of problems will it bring if you don't pay attention? Will it increase interference?

If the power supply is treated as a plane layer, the method should be similar to that of the ground layer. Of course, in order to reduce the common mode radiation of the power supply, it is recommended to shrink the height of the power layer from the ground layer by 20 times. If wiring, it is recommended to use a tree structure to avoid power loop problems. Power closed loop will cause large common mode radiation.

4. Should the address line use star wiring? If star wiring is used, can the Vtt terminal resistor be placed at the connection point of the star or at the end of a branch of the star?

Whether to use star wiring for the address line depends on whether the delay between the terminals meets the setup and hold time of the system, as well as the difficulty of wiring. The reason for the star topology is to ensure that the delay and reflection of each branch are consistent. Therefore, terminal parallel matching is used in star connection. Generally, matching is added to all terminals, and matching is added to only one branch, which cannot meet such requirements.

5. What effect does the pad have on high-speed signals?

A very good question. The impact of the pad on the high-speed signal is similar to the impact of the package of the device on the device. In a detailed analysis, after the signal comes out of the IC, it passes through the bonding wires, pins, package shells, pads, and solder to the transmission line. All joints in this process will affect the quality of the signal. But in actual analysis, it is difficult to give the specific parameters of the pad, solder and pin. Therefore, the package parameters in the IBIS model are generally used to summarize them. Of course, such analysis can be received at lower frequencies, and it is not accurate enough for higher-frequency signals and higher-precision simulations. A current trend is to use IBIS's VI and V-T curves to describe buffer characteristics, and to use SPICE models to describe package parameters. Of course, in IC design, there are also signal integrity issues, and the impact of these factors on signal quality is also considered in package selection and pin allocation.

6. In high-speed PCBs, VIA can reduce a large reflow path, but some people are willing to bend and do not use VIA. How should I choose?

Analyzing the return path of the RF circuit is not the same as the return path of the signal in the high-speed digital circuit. First of all, the two have something in common, both are distributed parameter circuits, and both use the maxwell equation to calculate the characteristics of the circuit.

However, the radio frequency circuit is an analog circuit, in which the voltage V=V(t) and the current I=I(t) both need to be controlled, while the digital circuit only pays attention to the change of the signal voltage V=V(t). Therefore, in RF wiring, in addition to considering signal return, it is also necessary to consider the influence of wiring on current. That is, whether the bending of the wiring and the via has any effect on the signal current.

In addition, most RF boards are single-sided or double-sided PCBs, and there is no complete plane layer. The return paths are distributed on various grounds and power supplies around the signal. 3D field extraction tools are required for analysis during simulation. The reflow of vias requires specific analysis; high-speed digital circuit analysis generally only deals with multi-layer PCBs with complete plane layers, using 2D field extraction analysis, only considering the signal reflow in adjacent planes, vias are only used as a lumped parameter R -L-C processing.

7. When the signal is divided across the power supply, does it mean that the AC impedance of the power plane is large for the signal? At this time, if the signal layer has a ground plane adjacent to it, even if the dielectric thickness between the signal and power layer is less than the dielectric thickness between the signal layer and the ground, will the signal choose the ground plane as the return path?