PCB Technical - What are the help of PCB design experience and skills

1. What is the meaning of each layer of the PCB circuit board?

Topoverlay ---- The name of the top device, also called top silkscreen or top component legend, such as R1 C5, IC10.

bottomoverlay-the same

multilayer-----If you design a 4-layer board, you place a free pad or via and define it as a multilay, then its pad will automatically appear on the 4 layers. If you only define it as the top layer, then it The pad will only appear on the top layer.

2. For a PCB with all digital signals, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), in order to ensure sufficient drive capacity, what kind of circuit should be used for protection?

To ensure the driving capability of the clock, it should not be achieved through protection, and the clock driving chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Adopt the clock to drive the chip, change one clock signal into several, adopt the point-to-point connection. When selecting the drive chip, in addition to ensuring that it is basically matched with the load, the signal edge meets the requirements (usually the clock is an edge valid signal). When calculating the system timing, the delay of the clock in the drive chip should be counted.

3. What aspects should be paid attention to when designing, routing and layout of high frequency PCB above 2G?

High-frequency PCBs above 2G belong to radio frequency circuit design and are not within the scope of discussion of high-speed digital circuit design. The layout and routing of the radio frequency circuit should be considered together with the schematic, because the layout and routing will cause distribution effects. (Maiwei Technology's high-speed PCB design training class is now available! First-line engineer lecturers teach hands-on, helping students quickly learn the basic skills of Cadence ORCAD/Allegro design from scratch) Moreover, some passive components in the RF circuit design are defined through parameterization and special shapes The realization of copper foil requires EDA tools to provide parametric devices and edit special-shaped copper foils.

Mentor's boardstation has a special RF design module that can meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The most famous in the industry is agilent's eesoft, which has a good interface with Mentor's tools.

4. 27M, SDRAM clock lines (80M-90M), the second and third harmonics of these clock lines happen to be in the VHF band, and the interference will be great after the high frequency enters from the receiving end. In addition to shortening the line length, what other good methods are there?

If the third harmonic is large and the second harmonic is small, it may be because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle.

In addition, if it is a unidirectional clock signal, the source terminal series matching is generally used. This can suppress secondary reflections, but will not affect the clock edge rate. The source matching value can be obtained using the formula below.

5. Please recommend an EDA software suitable for high-speed signal processing and transmission.

For conventional circuit design, INNOVEDA's PADS is very good, and there is a matching simulation software, and this type of design often occupies 70% of the applications. When doing high-speed circuit design, analog and digital hybrid circuits, the solution using Cadence should be a software with relatively good performance and price. Of course, Mentor's performance is still very good, especially its design flow management should be the best.

6. How to reduce EMI problems by arranging stacks?

First of all, EMI must be considered from the system. PCB alone cannot solve the problem.

For EMI, stacking is mainly to provide the shortest return path for the signal, reduce the coupling area, and suppress differential mode interference. In addition, the ground layer is tightly coupled with the power layer, which is more epitaxial than the power layer, which is good for suppressing common mode interference.

7. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?

The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board will increase the signal wiring length. And the grounding power supply of the single board is also a problem. If long-distance transmission is required, differential signals are recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and it is not necessary.

8. What is the topology of the wiring?

Topology, and some are also called routing order. The wiring order of the network connected with multiple ports.

9. How to adjust the routing topology to improve signal integrity?

This kind of network signal direction is more complicated, because for unidirectional, bidirectional signals, and different level types of signals, the topology influences are different, and it is difficult to say which topology is beneficial to the signal quality. And when doing pre-simulation, which topology to use is very demanding on engineers, requiring understanding of circuit principles, signal types, and even wiring difficulty.

10. What rules should be followed in the design of microstrip for high frequency PCB design above 2G?

The design of RF microstrip line requires 3D field analysis tools to extract the transmission line parameters. All rules should be specified in this field extraction tool.