PCB Technical - How to balance PCB power supply design

When designing a more complex PCB board, you have to make some design trade-offs. Because of these trade-offs, there are several factors that affect the design of a PCB's power distribution network.

How to balance PCB power supply design

When the capacitor is installed on the PCB, there is an additional loop inductance, which is related to the capacitor installation. The value of the loop inductance is design dependent. The inductance of the loop depends on the width and length of the line from the capacitor to the hole, the length of the line that connects the capacitor to the power/ground plane, the distance between the two holes, the diameter of the hole, the solder pad of the capacitor, etc. Figure 1 shows the installation graphics of various capacitors.

Key points in the design of reducing the inductance of capacitor circuit:

■ Holes should be placed as close to the capacitor as possible. Reduce the power/ground hole spacing. If possible, use multiple pairs of power supplies/ground holes in parallel. For example, the two holes with opposite polarity of current should be placed as close as possible, and the holes with the same polarity of current should be placed as far as possible.

■ Connect holes to capacitance pins with short, wide wires.

■ Place the capacitors on the surface of the PCB (top and bottom) as close as possible to their corresponding power/ground plane. This reduces the distance between the holes. Use a thin electrolyte between the power/ground.

Next are three different cases of design, for capacitor mounting and propagation inductance. FIG. 2 shows the introduction of inductance into the loop under various design conditions.

Case 1- Poor design

■ Designers do not focus on power distribution network (PDN) design.

■ Spacing of holes is not optimized.

■ The distance between power supply and ground plane is not optimized.

■ Long cable distance between the hole and capacitor pin.

For the overall loop inductance size, the loop inductance comes primarily from the line laid out, because the line length of the poor design is five times as long as the other two cases (good design and very good design). The distance from the base where the capacitor is installed to the near plane is also a major factor in the inductance size of the loop. Because this is not optimized (10mil), the effect of wiring on the inductance size of the entire loop is very large. Also, since the designer used 10mil of dielectric material between the power source and the ground, the secondary factor in the loop inductance comes from the propagation inductance. The distance between the holes without optimization is not as significant as the length of the holes. The effect of the hole becomes greater when the hole is longer.

Case 2- Good design

■ The designers focused on the design of a partial power distribution network (PDN).

■ Improved spacing of holes. The length of the hole remains the same.

■ Improved distance between power supply and ground level.

■ Wire distance from hole to capacitor pin is optimized.

The circuit inductance of the wire is still the main contributor to the overall circuit inductance. However, the inductance of the well-designed circuit is about 2.7 times smaller than that of the poorly designed circuit. Because the designers reduced the thickness of the dielectric from 10mil to 5mil, the propagation inductance was halved. The impact of the perforations is slightly improved by reducing the distance between the perforations.

■ Designers pay great attention to the design of PDN.

■ Improved spacing and length of holes.

■ The distance between power supply and ground has also been fully optimized.

■ Wire distance from hole to capacitor pin is optimized.

The inductance of a very good design is approximately 7.65 times less than that of a poor design. This is achieved by reducing the amount of thickness on the PCB from the bottom surface where the capacitor is installed to the near flat layer due to the reduced length of the wiring. Because the designers have optimized the thickness of the electrolyte layer between the power source and the ground, the propagation inductance is greatly reduced. As the hole spacing and hole length are greatly reduced, the loop inductance through the hole is also significantly improved. Compared with poor designs, the total loop inductance of very good designs is reduced by one of the seven major factors.

On the PCB, additional inductance through the hole loop is introduced by mounting the capacitor, thus reducing the resonant frequency of the capacitor. You must take this into account when designing a power distribution network (PDN). Reducing loop inductance is a visible way to reduce impedance when designing at high frequencies.

For a given power supply, the PDN tool produces a PCB that displays a very good design at a higher cutoff frequency than a very good design or a poor design. This may be the opposite of the expected result, because decoupling at higher cutoff frequencies requires more capacitance than decoupling at lower cutoff frequencies. In very well-designed cases, higher cutoff frequencies mean that higher frequencies can be decoupled. Capacitors placed on the PCB have a decoupling effect on noise up to a high frequency.

In the case of poor design, the PCB exceeding the lower cutoff frequency cannot be decoupled. Any additional capacitor addition, that is, adding a decoupling capacitor beyond the cutoff frequency only increases the BOM cost and has no effect on the decoupling effect. Compared with a very good design, the design of the power distribution network is more susceptible to noise at a particular frequency in the case of poor design. As another example, suppose a 20-layer PCB has a total thickness of 115mil. The power supply layer is on the third floor. The thickness from layer (the layer where the FPGA is) to layer 3 is 12mil. So the thickness from the bottom to the third layer is 103mil. The power source and the formation are separated by the dielectric after 3mil. The inductance size of the BGA hole for this kind of track is 5 nh (5 pairs of holes for this kind of power track). In order to cope with the close layout area of the layer, the decoupling capacitor associated with it is installed in the bottom layer. This tradeoff results in a very high inductance value for capacitor mounting due to the long perforations of such installations. After full optimization, the installed inductance of the 0402 package capacitor is 2.3nH at the bottom and 0.57nH at the same capacitor in the layer.

To improve this PDN effect for the track, you can place some high frequency capacitors in the layer, while keeping the mid frequency and bulk capacitors in their original position in the bottom layer. This circuit design is a cutoff solution for PDN because the high frequency capacitor is the capacitor that responds below the cutoff frequency. The effect of capacitance depends on the total loop inductance (capacitor mounting inductance + propagation inductance +BGA hole inductance) and FPGA. You can place the high frequency capacitor in the layer and slightly away from the FPGA. The propagation inductance of the capacitor placed outside the FPGA Breakout area is 0.2nh. This new placement method is beneficial compared to the original low-level placement method because of the total loop inductance (0.57nh + 0.2nh + 0.05nh =0.82nH) is smaller than the total inductance when placed in the bottom layer.

The propagation inductance of the PCB board is design dependent, it is uniformly present in the medium between the power supply and the ground plane. Thickness of 3mil or less is designed to reduce the plane propagation inductance. You can follow these design guidelines to improve PDN performance. Here are some design guidelines for sequential importance, layer to layer - design guidelines at layer are important.