PCB Technical - Quick and effective techniques for PCB flying probe testing

The test probe is connected to the driver (signal generator, power supply, etc.) and sensor (digital multimeter, frequency counter, etc.) through a multiplexing system to test the components on the UUT. When a component is being tested, other components on the UUT are electrically shielded by the prober to prevent reading interference. Flying probe test is one of the methods to check the electrical function of PCB (open and short circuit test). Flying tester is a system for testing PCB copy board in manufacturing environment. Instead of using all the traditional bed-of-nails interfaces on traditional online testing machines, flying probe testing uses four to eight independently controlled probes to move to the component under test. Unit under test (UUT, unit under test) is transported to the testing machine through a belt or other UUT transmission system. Then it is fixed, and the probe of the testing machine contacts the test pad and the via to test a single component of the UUT.

Steps of making PCB flying probe test program:

method one

First: Import the PCB layer file, check, arrange, align, etc., and then rename the two outer layers to fronrear. Change the name of the inner layer to ily02, ily03, ily04neg (if negative), rear, rearmneg.

Second: Add three layers, copy the two solder mask layers and the drilling layer to the added three layers, and change the name to fronmneg, rearmneg, mehole. Those with blind and buried vias can be named met01-02.,met02- 05, met05-06 and so on.

Third: Change the duplicated fronmneg and rearmneg to the round with the D code of 8mil. We call fronmneg the front test point and rearmneg the back test point.

Fourth: Delete the NPTH hole, find the via hole according to the line, and define the untested hole.

Fifth: Use fron and mehole as the reference layer, and change the fronmneg layer to on, and check to see if the test points are all in the window of the front layer. The test point in the hole larger than 100mil should be moved to the welding ring for testing. The test points at the BGA that are too dense must be misaligned. Some redundant intermediate test points can be deleted appropriately. The operation of the back layer is the same.

Sixth: Copy the organized test point fronmneg to the fron layer and rearmneg to the rear layer.

Seventh: Activate all layers and move to 10,10mm.

Eighth: The output gerber file is named fron, ily02, ily03, ily04neg, ilyo5neg, rear, fronmneg, rearmneg, mehole, met01-02, met02-09, and met09-met10 layers.

Then use Ediapv software

First: guide all gerber files like fron, ily02, ily03, ily04neg, ilyo5neg, rear, fronmneg, rearmneg, mehole, met01-02, met02-09, met09-met10 layers.

Second: Generate the network. net annotation of artwork button.

Third: Generate test files. Make test programs button, enter the D code of the untested hole.

Fourth: save.

Fifth: Set the reference point and you are done. Then take it to the flying probe machine and test it.

Summarize:

1. PCB factories often make many test points in this method for test files, and the intermediate points cannot be deleted automatically.

2 If there is a MEHOLE window on both sides, but there are measuring points on both sides, you can press the make test programs button again. Note that you can place the cursor above the MEHOLE layer.

3. Poor grasp of the hole test. View the generated connectivity (open circuit) test points in ediapv, there is no test point for a single hole. Another example: there is a line on one side of the hole and no line on the other side. It is reasonable to test the hole on the side without a line. However, the test points generated by ediapv conversion are random, and sometimes they are right or wrong.

4. For the REAR surface solder mask without window opening, the name of the REAR layer can be named as another name, so that in EDIAPV, it will not run out of the test point inexplicably.