PCB Technical - What to do when PCB design impedance cannot be continuous

How to suppress crosstalk in PCB design and what to do when PCB design impedance cannot be continuous

How to suppress crosstalk in PCB design

A changed signal (such as a step signal) propagates along the transmission line from A to B. A coupled signal will be generated on the transmission line CD. Once the changed signal ends, that is, when the signal returns to a stable DC level, the coupled signal will not exist, so crosstalk It only occurs in the process of signal transitions, and the faster the signal edge changes (conversion rate), the greater the crosstalk generated.

The electromagnetic field coupled in space can be extracted as a collection of countless coupling capacitors and coupling inductances. The crosstalk signal generated by the coupling capacitor can be divided into forward crosstalk and reverse crosstalk Sc on the victim network. These two signals have the same polarity; The crosstalk signal generated by the inductance is also divided into forward crosstalk and reverse crosstalk SL, and these two signals have opposite polarities.

The forward crosstalk and reverse crosstalk generated by the coupled inductance and capacitance exist at the same time and are almost equal in size. In this way, the forward crosstalk signals on the victim network cancel each other due to the opposite polarity, and the reverse crosstalk polarity is the same, and the superposition is enhanced. The modes of crosstalk analysis usually include default mode, three-state mode and worst-case mode analysis.

The default mode is similar to the way we actually test the crosstalk, that is, the offending network driver is driven by a flip signal, and the victim network driver maintains the initial state (high level or low level), and then the crosstalk value is calculated. This method is more effective for crosstalk analysis of unidirectional signals. The tri-state mode means that the driver of the offending network is driven by a flip signal, and the tri-state terminal of the victim network is set to a high-impedance state to detect the size of the crosstalk. This method is more effective for two-way or complex topology networks. The worst-case analysis refers to keeping the driver of the victim network in the initial state, and the simulator calculates the sum of the crosstalk of all the default infringement networks to each victim network.

This method generally only analyzes individual key networks, because there are too many combinations to be calculated and the simulation speed is relatively slow.

There are always several places where the impedance cannot be continuous in PCB design. What should I do?

Everyone knows that the impedance must be continuous. However, as Luo Yonghao said, "There are always times when you step on the stool in your life", there are always times when the impedance cannot be continuous in PCB design. How to do?

Characteristic impedance: also known as "characteristic impedance", it is not a DC resistance, it belongs to the concept of long-term transmission. In the high frequency range, during signal transmission, where the signal edge arrives, an instant current will be generated between the signal line and the reference plane (power or ground plane) due to the establishment of an electric field.

If the transmission line is isotropic, then as long as the signal is transmitting, there will always be a current I, and if the output voltage of the signal is V, the transmission line will be equivalent to a resistance during the signal transmission, the size of which is V/I, Call this equivalent resistance the characteristic impedance Z of the transmission line.

In the process of signal transmission, if the characteristic impedance on the transmission path changes, the signal will be reflected at the node where the impedance is discontinuous.

The factors that affect the characteristic impedance of the PCB are: dielectric constant, dielectric thickness, line width, and copper foil thickness.

[1] Gradient line

Some RF device packages are small, SMD pad width may be as small as 12 mils, and RF signal line width may reach 50 mils or more. Gradient lines must be used, and line width mutations are prohibited.

[2] corner

If the RF signal line runs at a right angle, the effective line width at the corner will increase, and the impedance will be discontinuous, causing signal reflection. In order to reduce the discontinuity, to deal with the corners, there are two methods: chamfering and rounding. The radius of the arc angle should be large enough, generally speaking, to ensure: R>3W.

【3】Large pad

When there are large pads on the 50-ohm microstrip line, the large pads are equivalent to distributed capacitance, which destroys the characteristic impedance continuity of the microstrip line. Two methods can be taken to improve at the same time: firstly, thickening the microstrip line dielectric, and secondly, hollowing out the ground plane under the pad, which can reduce the distributed capacitance of the pad.

【4】via

Vias are metal cylinders plated outside the through holes between the top and bottom layers of the circuit board. Signal vias connect transmission lines on different layers. The via stub is the unused part of the via. Via pads are ring-shaped spacers that connect the via to the top or internal transmission line. Isolation disks are annular gaps in each power or ground plane to prevent short circuits to the power and ground planes.

Parasitic parameters of vias

After rigorous physical theory derivation and approximate analysis, the equivalent circuit model of the via can be a grounded capacitor connected in series at both ends of an inductor, as shown in Figure 1.

Equivalent circuit model of via

It can be seen from the equivalent circuit model that the via itself has parasitic capacitance to ground. Assume that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately:

The parasitic capacitance of the via can cause the signal rise time to be prolonged and the transmission speed to slow down, thereby deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than parasitic capacitance.

Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center hole. The approximate parasitic inductance of the via is similar to:

Vias are one of the important factors that cause impedance discontinuities on the RF channel. If the signal frequency is greater than 1GHz, the impact of vias must be considered.

Common methods to reduce the discontinuity of via impedance include: adopting a diskless process, selecting an outlet method, and optimizing the diameter of the anti-pad. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuities. Since the characteristics of vias are related to the structural dimensions such as aperture, pad, anti-pad, laminated structure, and wiring method, it is recommended that HFSS and Optimetrics be used for optimization simulation according to the specific situation during each design.

When using a parametric model, the modeling process is simple. During the review, PCB designers are required to provide corresponding simulation documents.

The diameter of the via, the diameter of the pad, the depth, and the anti-pad will all bring changes, resulting in impedance discontinuity, reflection and insertion loss severity.

【5】Through hole coaxial connector

Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as that of the via. Commonly used methods to reduce the impedance discontinuity of through-hole coaxial connectors are also: adopting a diskless process, a suitable outlet method, and optimizing the diameter of the anti-pad.