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In high-speed PCB boards, routing is more than just connecting two points. As a qualified engineer, wiring is a mixed knowledge carrier including resistance, capacitance and inductance. The signal line will reflect during transmission. This must be understood. The magnitude of the reflection at the load end depends on the Z of the transmission line and the Z of the load.
The magnitude of the signal reflected is measured by the reflection coefficient KR. The reflection coefficient at the load end is: KRL=(ZL-Z0)/(ZL+Z0), for an open circuit load, KRL=1; for a short circuit load, KRL=-1 is visible, For open-circuit and short-circuit loads, the signal is 100% reflected back. A negative value of KRL indicates that the reflected signal is in the opposite direction to the original signal. Similarly, the magnitude of signal reflection at the source end is expressed by the reflection coefficient of the source end: KRS=(ZS-Z0)/(ZS+Z0).
The PCB factory sets the standard output level of the driver to be 0.2V and the current is 24mA, so its output impedance ZS is about 8.3 Ω. Assuming that the input impedance ZL of the load is greater than 100KΩ and much larger than Z0 (about 67Ω), the reflection coefficient at the load end is: KRL=1, and the signal is 100% reflected at the load end. The source reflection coefficient is KRS=-0.78. Provide online components, sensor procurement, PCB customization, BOM distribution, material selection and other electronic industry supply chain complete solutions, one-stop to meet the comprehensive needs of small and medium-sized customers in the electronics industry.
Let's analyze the reflection process of the driver switching from 3.5V to 0.2V.
The first reflection: The driver voltage is 3.3V. According to the principle of voltage division composed of ZS and Z0, the signal generated on Z0 is △V=-2.94V, and the source terminal signal voltage is VS=0.56V. The reflection coefficient at the load end is 1. When the signal reaches the load end, VL=3.5-2.94-2.94=-2.38V.
Second reflection: The first source signal is 0.56V. When the -2.94V signal reaches the source, the second reflection occurs. The reflected voltage is: VR=KPS*△V =-0.78*(-2.94)=2.29V. So the source terminal voltage becomes VS=0.56+(-2.94)+2.29=-0.09V.
The third reflection: When the second reflection signal reaches the load terminal, the load terminal voltage becomes VL =-2.38+2.29+2.29=2.2.V
On this kind of impedance mismatched transmission line, the signal is reflected back and forth in this way, and its amplitude decreases a little after each reflection, until it finally disappears. The vertical lines on the left and right represent the voltages at the source and load, respectively, and the oblique lines indicate the magnitude of the transmitted signal and the reflected signal voltage. It can also be used to indicate the specific reflection process of the signal, one for the source end signal and the other for the load end signal. It can be seen that after 5 cycles, the signal transmitted to the load end drops below the input threshold. The transmission delay is generally between 6-16ns/m. If the transmission delay tPD=10ns/m, then pass The delay of a 0.15m transmission line is about 1.5ns, so the signal can be considered valid after about 13.5ns is transmitted.
The above is how to solve signal reflection in high-speed PCB circuit board design
