PCB Blog - Routing technology improves the integrity of embedded PCB board

1 Introduction
Printed circuit boards are the basic support of circuit components and devices in electronic products, and its design quality often directly affects the reliability and compatibility of embedded systems. In the past, in some low-speed circuit boards, the clock frequency was generally only about 10 MHz. The main challenge of circuit board or package design was how to route all signal lines on the double-layer board and how to assemble without destroying the package. The electrical characteristics of the interconnects are not critical since the interconnects have not affected system performance. In this sense, the interconnect lines in the signal low-speed circuit board are unobstructed and transparent. However, with the development of embedded systems, the circuits used are basically high-frequency circuits. Due to the increase of the clock frequency, the rising edge of the signal is also shortened, and the capacitive and inductive reactance of the printed circuit to the passing signal will be much greater than The resistance of the printed circuit itself seriously affects the integrity of the signal. For embedded systems, signal integrity effects become important when clock frequencies exceed 100 MHz or rising edges are less than 1 ns. This paper starts from the actual electrical characteristics of signal lines in high-speed digital circuits, establishes an electrical characteristics model, finds the main reasons that affect signal integrity and how to solve the problems, and gives the problems that should be paid attention to in the wiring and the methods and skills to follow.

2. Signal integrity
Generally, it can be considered that signal integrity should include the following meanings: the waveform distortion of the signal should be controlled within a certain range, the timing diagram of the signal flow can meet the logic requirements, and the signal generation and transmission process is stable in the burst state. The destruction of signal integrity is mainly due to two reasons. First, due to external interference, especially the interference of the conduction channel, including the reflection effect caused by the impedance mismatch of the transmission channel, the original waveform is destroyed; secondly, the digital signal will naturally A spectral dispersion effect occurs, changing the original waveform. When the clock frequency is relatively high, such as when the clock reaches 10MHz or more or the edge time of the pulse reaches 1ns or less, we will find that it is not easy to get the signal to where it is expected. There are many factors that affect signal integrity issues, including jitter, delay, ground bounce, reflections, crosstalk, switching noise, power supply mismatch, attenuation, pulse stretching, timing confusion, etc. Signal integrity issues always involve the entire process of the signal, so signal integrity assurance requires the physical environment in which the entire signal works. To do this, it is necessary to model the signal integrity system. The signal integrity system model should include three parts: the complete signal source, the physical coordination channel of the signal, and the complete reception of the signal. The main contents of the three parts are as follows:
(1) Complete signal source: ensure the integrity of the generated signal. These include power supply guarantee, noise filtering, ground potential, common mode elimination, output impedance guarantee, etc.
(2) The physical coordination channel of the signal: Ensure that the signal does not change during transmission. These include: crosstalk, delays, channel dips, reflections and resonances, bandwidth, attenuation, impedance control, circuit linking, and more.
(3) Complete signal reception: ensure high-efficiency reception without distortion. These include: input impedance matching, grounding processing, multi-terminal network mutual impedance, decoupling capacitors, filter capacitors, input network signal distribution and signal protection issues

2.1 Delay: Delay means that the signal is transmitted at a limited speed on the transmission line of the PCB board. The signal is sent from the sender to the receiver, and there is a transmission delay in between. Signal delays have an impact on the timing of the system; propagation delays are primarily determined by the length of the wire and the dielectric constant of the medium surrounding the wire. In a high-speed digital system, the length of the signal transmission line is a direct factor that affects the phase difference of the clock pulses. The phase difference of the clock pulses refers to the asynchronous time when the two clock signals generated at the same time arrive at the receiving end. The clock pulse phase difference reduces the predictability of the arrival of the signal edge, and if the clock pulse phase difference is too large, it will produce an erroneous signal at the receiving end.

2.2 Reflection: Reflection is the echo of the signal on the signal line. When the signal delay time is much greater than the signal transition time, the signal line must be used as a transmission line. When the characteristic impedance of the transmission line does not match the load impedance, a portion of the signal power (voltage or current) is transmitted to the line and reaches the load, but a portion is reflected. If the load impedance is smaller than the original impedance, the reflection is negative; otherwise, the reflection is positive. Variations in trace geometry, incorrect wire termination, transmission through connectors, and power plane discontinuities can all cause such reflections.

2.3 Crosstalk: Crosstalk is the coupling between two signal lines, the mutual inductance and mutual capacitance between the signal lines, and the noise on the signal line. Capacitive coupling induces coupling current, while inductive coupling induces coupling voltage. Crosstalk noise originates from electromagnetic coupling between signal lines, between signal systems and power distribution systems, and between vias. Cross-winding may cause false clocks, intermittent data errors, etc., and affect the transmission quality of adjacent signals. In reality, crosstalk cannot be completely eliminated, but it can be controlled within the range that the system can tolerate. The parameters of the PCB layer, the distance between the signal lines, the electrical characteristics of the driving end and the receiving end, and the baseline termination method all have a certain influence on the crosstalk. When wiring high-speed PCB boards, if the wiring space is small or the wiring density is high, the problem of crosstalk is very serious, and the electromagnetic interference caused by it will seriously affect the signal of the circuit. In order to reduce crosstalk, the following measures can be taken during wiring: properly terminate the crosstalk-sensitive signal lines, and reduce the crosstalk by reducing the coupling capacitance through impedance matching.

2.4 Overshoot and undershoot: Overshoot is a peak or valley value exceeding the set voltage. For the rising edge, it refers to the voltage; for the falling edge, it refers to the voltage. Undershoot is when the next valley or peak exceeds the set voltage. Excessive overshoot can cause the protection diode to operate, causing it to fail prematurely. Excessive undershoot can cause spurious clock or data errors (misoperations).

2.5 Oscillation and Surround Oscillation: Oscillation phenomena are repeated overshoots and undershoots. The oscillation of the signal is the oscillation caused by the inductance and capacitance of the transition on the line, which belongs to the under-damped state, while the surrounding oscillation belongs to the over-damped state. Oscillation and surround oscillations, like reflections, are caused by many factors, and oscillations can be reduced by proper termination, but cannot be completely eliminated. Ground bounce noise and return noise: When there is a large current surge in the circuit, it will cause ground bounce noise. For example, when the outputs of a large number of chips are turned on at the same time, there will be a large transient current between the chip and the board. The inductance and resistance of the chip package and the power plane will cause power supply noise, which will cause voltage fluctuations and changes on the true ground plane, and this noise will affect the behavior of other components. The increase of the load capacitance, the decrease of the load resistance, the increase of the ground inductance, and the increase of the number of switching devices will all lead to the increase of the ground bounce.

3. Analysis of the electrical characteristics of the transmission channel
In a multi-layer PCB board, most of the transmission lines are not only arranged on a single layer, but staggered on multiple layers, and the layers are connected through vias. Therefore, in a multi-layer PCB board, a typical transmission channel mainly includes three parts: transmission line, trace corner, and via hole. In the case of low frequency, printed lines and trace vias can be regarded as ordinary electrical connections connecting pins of different devices, which will not have much impact on signal quality. However, at high frequencies, traces, corners and vias should not only consider their connectivity, but also the influence of their electrical characteristics and parasitic parameters at high frequencies.

4. Analysis of electrical characteristics of transmission lines in high-speed PCB boards
In the design of high-speed PCB board, it is inevitable to use a large number of signal connecting lines, and the lengths are different. The delay time of the signal passing through the connecting line can not be ignored compared with the change time of the signal itself, and the signal is transmitted at the speed of electromagnetic waves. For upstream transmission, the connection line at this time is a complex network with resistance, capacitance, and inductance, which needs to be described by a distributed parameter system model, that is, the transmission line model. A transmission line is used to transmit a signal from one end to the other and consists of 2 wires with a certain length, one is called the signal path and the other is called the return path. In low frequency circuits, transmission lines behave as purely resistive electrical properties. In high-speed PCB boards, as the frequency of the transmission signal increases, the capacitive impedance between the wires decreases, and the inductive impedance on the wires increases, and the signal wire will no longer behave as a pure resistance, that is, the signal will not only be transmitted on the wire, but also It also propagates in the medium between conductors. For a uniform wire, the resistance R, the parasitic inductance L and the parasitic capacitance C of the transmission line are evenly distributed (ie, L1=L2=…=Ln; C1=C2=…=Cn+1) without considering the external environment change.

5. Analysis of electrical characteristics of vias in high-speed PCB boards
Via, usually refers to a hole in a printed circuit board, is an important factor in the design of multi-layer PCB boards. Vias can be used for fixed installation of plug-in components or interconnection between layers. From a process perspective, vias are generally divided into three categories: blind vias, buried vias, and through vias. Blind holes are located on the top and bottom surfaces of the printed circuit board, with a certain depth, and are used for the connection of the surface layer circuit and the underlying inner layer circuit. The depth of the hole and the diameter of the hole usually do not exceed a certain ratio. Buried vias refer to connection holes located in the inner layer of the printed circuit board, which do not extend to the surface of the circuit board. Through-holes pass through the entire circuit board and can be used for interconnection between layers or as mounting holes for components. Because the through hole is easier to realize in the process and the cost is lower, the general printed circuit board uses the through hole instead of the other two kinds of through holes. The via holes mentioned below are considered as through holes. As a special transmission line, vias not only generate parasitic capacitance to ground, but also parasitic inductance in high-speed circuits. The impact of the parasitic capacitance of the via on the circuit is mainly to slow down or deteriorate the rising edge of the digital signal, reducing the speed of the circuit. The smaller the parasitic capacitance value of the via, the smaller the impact. The main effect of the via parasitic inductance is to reduce the effectiveness of the power supply bypass capacitor and make the entire power supply filtering effect worse.

6. Contribution of transmission line corners to transmission channel signal integrity problems
When the printed line of the PCB board passes through the corner, the change of the width of the printed line is yes, and the characteristic impedance of the printed line also changes. Since the width of the trace becomes wider when it passes the corner, the capacitance between the trace and the reference layer increases, and the characteristic impedance of the trace decreases. Therefore, there is a discontinuity of characteristic impedance at the corner of the printed line, which leads to the reflection of the signal on the printed line and affects the signal integrity. Comparison of reflection and transmission characteristics of corners of different geometric shapes: Common PCB board printed line corner geometries: Right-angled corners, rounded corners, inside and outside 45-degree beveled corners, and 45-degree outside beveled corners. The reflection and transmission characteristics of the corners of traces of different geometries are different. The order of excellent transmission characteristics is as follows: right angle < rounded corner < 45 degree bevel cut inside and outside < 45 degree outer bevel cut, and the corner geometry of the printed line is right-angle bend and 45 degree outer bevel cut. Below the frequency range of 2GH, the track corner geometry has little effect on the signal transmission characteristics, and its effect increases significantly as the frequency increases, especially for right-angled corners. It is recommended that the corners of the trace be bent at a right angle with a 45-degree beveled geometry, which itself has less impact on signal integrity. When the signal line width is narrow in a high-density circuit board, the delay accumulation caused by the parasitic capacitance of the corner is generally unlikely to have a great impact on the signal integrity. But for high-frequency sensitive circuits, such as high-frequency clock lines, the cumulative effect of corner parasitic capacitance should be considered.

7. Use wiring techniques to suppress signal integrity issues
When the signal is output from the drive source, the currents and voltages that make up the signal treat the interconnect as an impedance network. As the signal propagates along the impedance network, it constantly experiences transient impedance changes caused by the interconnect. If the impedance seen by the signal remains the same, the signal is not distorted. Once the impedance changes, the signal is reflected at the change and distorted as it travels through the rest of the interconnect. If the impedance changes sufficiently, the distortion can cause false triggering. In the signal integrity optimization design process, an important design goal is to design all interconnect lines as uniform transmission lines, and reduce the length of all non-uniform transmission lines, so that the impedance felt by the signals in the entire network remains unchanged. . Based on this, it can be concluded that some methods of using wiring techniques to suppress signal integrity problems: the trace shape of the printed conductors should not be tangled, branched or hard corners, try to avoid T-shaped lines and stubs; try to keep the same network signal line. Line width, reduce line width change; reduce transmission line length, increase wire width; try to increase the distance between wires; try to reduce the vias and corners of high-speed signal lines, and reduce the inter-layer conversion of signal lines; reasonable selection of vias size; reduce signal loop area and loop current. In conclusion, any feature that changes the cross-section or network geometry will change the impedance seen by the signal. The key to reducing signal integrity problems in cabling is to reduce the sudden change of impedance on the transmission line, so that the impedance experienced by the signal in the entire network remains unchanged. In short, in the design of the PCB board, it is necessary to integrate the layout and wiring of the components and the solution to the signal integrity problem that should be used in each case, so as to better solve the signal integrity problem of the PCB board.

8. Conclusion
In today's wide application of embedded systems, signal integrity has become an extremely important content in the PCB board design of embedded systems, affecting the success or failure of the entire PCB board design. When the circuit is determined, the components are selected, and the PCB layout is determined, wiring techniques can be used to suppress the occurrence of signal integrity problems, improve the reliability of the PCB board, and reduce the loss caused by signal integrity problems. Aiming at the signal integrity problem caused by the high frequency environment of the embedded system PCB board, this paper proposes a method to suppress it by reasonable wiring. Through the analysis of various signal integrity phenomena and the modeling and description of the electrical characteristics of transmission lines, vias and corners, some methods for improving signal integrity by using wiring skills in PCB board design are concluded, which have practical reference value.