PCB Blog - The role of layered stacking of PCB boards in controlling EMI radiation

This article starts from basic PCB board layout and discusses the role and design techniques of layered PCB board stacking in controlling EMI radiation. There are many ways to solve the EMI problem. Modern EMI suppression methods include: the use of EMI suppression coatings, the selection of appropriate EMI suppression spare parts and EMI simulation design.

1. Power busbar
Reasonable placement of capacitors with appropriate capacity near the power pins of the IC can make the IC output voltage jump faster. However, the problem does not end there. Due to the finite frequency response of capacitors, this prevents them from generating the harmonic power needed to cleanly drive the IC's output over the full frequency band. In addition, the transient voltages developed on the power busbars will create a voltage drop across the inductance of the decoupling path, and these transient voltages are the main source of common-mode EMI interference. How should we solve these problems? In the case of an IC on our board, the power plane around the IC can be thought of as a good high-frequency capacitor that harvests the energy leaked by the discrete capacitors that provide high-frequency energy for a clean output. In addition, the inductance of a good power supply layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common mode EMI. Of course, the connection from the power supply layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, and it is directly connected to the pad where the IC power supply pin is located, which will be discussed separately. To control common-mode EMI, the power plane must be a reasonably well-designed pair of power planes to facilitate decoupling and have sufficiently low inductance. One might ask, how good is it? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (ie, a function of the IC's rise time). Usually, the spacing of the power layer is 6mil, and the interlayer is FR4 material, the equivalent capacitance per square inch of the power layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance. There are not many devices with rise times of 100 to 300ps, but at the current rate of development of ICs, there will be a high proportion of devices with rise times in the range of 100 to 300ps. For circuits with rise times of 100 to 300ps, 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layering techniques with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Now, ceramics and ceramics can meet the design requirements of 100 to 300ps rise time circuits. Although new materials and methods may be adopted in the future, for today's common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and keep transients low enough to be That said, common mode EMI can be very low. The PCB board layered stack design example given in this article will assume a layer spacing of 3 to 6 mils.

2. Electromagnetic shielding
From the signal routing point of view, a good layering strategy should be to place all signal traces on one or several layers next to power or ground planes. For power, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible, which is what we call the "layering" strategy.

3. 4-layer board
There are several potential issues with the 4-layer board design. First of all, for a traditional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large. If cost requirements are in place, consider the following two alternatives to traditional 4-layer boards. Both solutions can improve EMI suppression performance, but only when the component density on the board is low enough and there is enough area around the components (to place the required power supply copper layer). The outer layers of the PCB are ground layers, and the two middle layers are signal/power layers. The power supply on the signal layer is routed with wide traces, which makes the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low. From an EMI control perspective, this is an existing 4-layer PCB board structure. In the second scheme, the outer layer takes the power and ground, and the middle two layers take the signal. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as the traditional 4-layer board. If trace impedance is to be controlled, the above stacking schemes require very careful routing of traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as closely as possible to ensure DC and low frequency connectivity.

4. 6-layer board
If the component density on a 4-layer board is relatively high, a 6-layer board is used. However, some stacking schemes in the 6-layer board design are not good enough to shield the electromagnetic field, and have little effect on reducing the transient signal of the power busbar. Two examples are discussed below. For example, the power supply and the ground are placed on the second and fifth layers respectively. Due to the high impedance of the power supply copper cladding, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of impedance control of the signal, this method is quite correct. The second example places power and ground on the 3rd and 4th layers, respectively. This design solves the problem of power supply copper cladding impedance. Due to the poor electromagnetic shielding performance of the 1st and 6th layers, the differential mode EMI increases. If the number of signal lines on the two outer layers is low and the trace length is short (shorter than 1/20 the wavelength of the signal harmonic), this design can solve the differential mode EMI problem. The suppression of differential mode EMI is particularly good by filling the non-component and non-trace areas on the outer layer with copper and grounding the copper area (every 1/20 wavelength is an interval). As mentioned earlier, the copper area should be connected to the internal ground plane at multiple points. The general high-performance 6-layer board design generally arranges the 1st and 6th layers as ground layers, and the 3rd and 4th layers take power and ground. EMI suppression is excellent due to two centered dual microstrip signal line layers between the power and ground planes. The disadvantage of this design is that there are only two layers of traces. As mentioned earlier, the same stackup can be achieved with a traditional 6-layer board if the outer layer traces are short and copper is placed in the no-trace area. Another 6-layer board layout is signal, ground, signal, power, ground, signal, which enables the environment required for signal integrity designs. The signal layer is adjacent to the ground plane, and the power and ground planes are paired. Obviously, the downside is the unbalanced stacking of layers. This usually causes trouble in manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power layer or the ground layer after copper filling, this board can be loosely counted as a structurally balanced circuit board. . The copper filling area must be connected to power or ground. The distance between the connecting vias is still 1/20 wavelength, not necessarily everywhere, but ideally should be connected.

5. 10-layer board
Because the insulating layers between the multilayer boards are very thin, the impedance between layers of a 10- or 12-layer board is very low, and excellent signal integrity can be expected as long as there are no problems with delamination and stacking. It is more difficult to manufacture 12-layer boards with a thickness of 62 mil, and there are not many manufacturers that can process 12-layer boards. Since there is always an insulating layer between the signal layer and the loop layer, the solution of allocating the middle 6 layers to route the signal lines in the 10-layer board design is not. Also, it is important to have the signal layer adjacent to the loop layer, i.e. the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal. This design provides a good path for the signal current and its loop current. A proper routing strategy is to route the first layer along the X direction, the third layer along the Y direction, the fourth layer along the X direction, and so on. Looking at the traces intuitively, layers 1 and 3 are a pair of layered combinations, layers 4 and 7 are a pair of layered combinations, and layers 8 and 10 are a pair of layered combinations. When it is necessary to change the direction of the traces, the signal lines on the first layer should be "via holes" to the third layer and then change the direction. In practice, it may not always be possible to do so, but as a design concept try to adhere to it. Likewise, when the routing direction of the signal is changed, it should be via vias from layers 8 and 10 or from layer 4 to layer 7. This routing ensures tight coupling between the forward path and the return path of the signal. For example, if the signal is routed on layer 1 and the loop is routed on layer 2 and only on layer 2, even if the signal on layer 1 goes to layer 3 through a "via", its The loop is still on layer 2, thus maintaining low inductance, high capacitance, and good electromagnetic shielding performance. What if the actual wiring is not like this? For example, the signal line on the first layer goes through the via hole to the tenth layer. At this time, the loop signal has to find the ground plane from the ninth layer, and the loop current needs to find the nearest ground via hole (such as the ground pins of components such as resistors or capacitors) . If you happen to have such a via nearby, you're really lucky. If there are no such close vias available, the inductance will increase, the capacitance will decrease, and the EMI will definitely increase. When the signal line must leave the current pair of wiring layers to other wiring layers through vias, ground vias should be placed near the vias, so that the loop signal can smoothly return to the appropriate grounding layer. For layer 4 and layer 7 layered combination, the signal loop will return from the power layer or the ground layer (ie layer 5 or layer 6), because the capacitive coupling between the power layer and the ground layer is good, the signal is easy to transmit .

6. Design of Multiple Power Layers
If the two power planes of the same voltage source need to output a large current, the circuit board should be laid out in two sets of power planes and ground planes. In this case, insulating layers are placed between each pair of power and ground planes. In this way, we get the two pairs of power bus bars with equal impedance that we expect to divide the current equally. If the stacking of power planes creates unequal impedances, the shunting will not be uniform, the transient voltage will be much larger, and EMI will increase dramatically. If there are multiple supply voltages with different values on the board, then multiple power planes are required, keeping in mind to create their own paired power and ground planes for the different power supplies. In both cases above, keep in mind the manufacturer's requirements for a balanced structure when determining the placement of the mating power and ground planes on the board.

7. Summary
Given that most engineers design boards as conventional printed circuit boards with a thickness of 62 mils and no blind or buried vias, this discussion of board layering and stacking is limited to that. For boards with too different thicknesses, the layering scheme recommended in this article may not be ideal. In addition, circuit boards with blind or buried vias are processed differently, and the layering approach in this paper is not applicable. The thickness, via process and the number of layers of the circuit board in the circuit board design are not the key to solving the problem. Excellent layered stacking is to ensure the bypass and decoupling of the power busbar, so that the transient voltage on the power plane or ground plane is not affected. The key to shielding the electromagnetic fields of signals and power. Ideally, there should be an insulating isolation layer between the signal trace layer and its return ground layer, and the paired layer spacing (or more than one pair) should be as small as possible. Based on these basic concepts and principles, printed circuit boards that can always meet the design requirements can be designed.