With the increase in the output switching speed of integrated circuits and the increase in the density of
PCB board, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB boards, and the layout of components on the PCB board , the wiring of high-speed signal lines and other factors will cause signal integrity problems.
For PCB layout, signal integrity requires providing a board layout that does not affect signal timing or voltage, while for circuit routing, signal integrity requires providing termination components, placement strategies, and routing information. High signal speed on the PCB, incorrect placement of termination components, or incorrect wiring of high-speed signals can cause signal integrity problems, which may cause the system to output incorrect data, the circuit to work abnormally or even not work at all. Fully considering the factors of signal integrity in the design process and taking effective control measures have become a hot topic in the PCB design industry today.
1. Signal integrity issues
Good signal integrity means that the signal responds with the correct timing and voltage level values when needed. Conversely, a signal integrity problem occurs when the signal does not respond properly. Signal integrity problems can cause or directly lead to signal distortion, timing errors, incorrect data, address and control lines, and system malfunctions, and even system crashes. Caused by a combination of factors. The switching speed of the IC, incorrect placement of termination components, or incorrect routing of high-speed signals can all cause signal integrity issues. Major signal integrity issues include: delays, reflections, synchronous switching noise, oscillations, ground bounce, crosstalk, etc.
2. Definition of Signal Integrity
Signal integrity refers to the ability of the signal to respond with the correct timing and voltage in the circuit. It is a state in which the signal is not damaged. It indicates the quality of the signal on the signal line.
2.1 Delay
Delay means that the signal is transmitted at a limited speed on the wires of the PCB board. The signal is sent from the sender to the receiver, and there is a transmission delay in between. The delay of the signal will affect the timing of the system, and the propagation delay mainly depends on the length of the wire and the dielectric constant of the medium around the wire. In a high-speed digital system, the length of the signal transmission line is a direct factor that affects the phase difference of the clock pulses. The phase difference of the clock pulses refers to two clock signals generated at the same time, and the time when they arrive at the receiving end is not synchronized. The clock pulse phase difference reduces the predictability of the arrival of the signal edge. If the clock pulse phase difference is too large, an erroneous signal will be generated at the receiving end. As shown in Figure 1, the transmission line delay has become an important part of the clock pulse cycle.
2.2 Reflection
The reflection is the echo on the sub-transmission line. When the signal delay time (Delay) is much greater than the signal transition time (Transition Time), the signal line must be used as a transmission line. When the characteristic impedance of the transmission line does not match the load impedance, part of the signal power (voltage or current) is transmitted to the line and reaches the load, but part of it is reflected. If the load impedance is smaller than the original impedance, the reflection is negative; otherwise, the reflection is positive. Variations in trace geometry, incorrect wire termination, transmission through connectors, and power plane discontinuities can all cause such reflections.
2.3 SSN
When many digital signals on the PCB are switched synchronously (such as the data bus of the CPU, the address bus, etc.), due to the impedance on the power line and the ground line, synchronous switching noise will be generated, and the ground plane will bounce on the ground line. Noise (ground bounce). The strength of the SSN and ground bounce also depends on the I/O characteristics of the integrated circuit, the impedance of the power supply layer and the plane layer of the PCB, and the layout and routing of the high-speed devices on the PCB.
2.4 Crosstalk
Crosstalk is the coupling between two signal lines, and the mutual inductance and mutual capacitance between the signal lines cause noise on the line. Capacitive coupling induces coupling current, while inductive coupling induces coupling voltage. Crosstalk noise originates from electromagnetic coupling between signal lines, between signal systems and power distribution systems, and between vias. Crosstalk may cause false clocks, intermittent data errors, etc., affecting the transmission quality of adjacent signals. In fact, we do not need to completely eliminate the cross-winding, as long as it is controlled within the range that the system can bear. The parameters of the PCB layer, the distance between the signal lines, the electrical characteristics of the driving end and the receiving end, and the baseline termination method all have a certain influence on the crosstalk.
2.5 Overshoot and Undershoot
Overshoot is a peak or valley value exceeding the set voltage, for rising edges, it refers to voltage, and for falling edges, it refers to voltage. Undershoot is when the next valley or peak exceeds the set voltage. Excessive overshoot can cause the protection diode to operate, causing it to fail prematurely. Excessive undershoot can cause spurious clock or data errors (misoperations).
2.6 Ringing and Rounding
Oscillation is the repeated overshoot and undershoot. The oscillation of the signal is the oscillation caused by the inductance and capacitance of the transition on the line, which belongs to the under-damped state, while the surrounding oscillation belongs to the over-damped state. Oscillation and surround oscillations, like reflections, are caused by many factors, and oscillations can be reduced by proper termination, but cannot be completely eliminated.
2.7 Ground bounce noise and return noise
When there is a large current surge in the circuit, it will cause ground plane bounce noise. For example, when the outputs of a large number of chips are turned on at the same time, a large transient current will flow through the power plane of the chip and the board, and the chip package and the power supply The inductance and resistance of the planes cause power supply noise, which creates voltage fluctuations and changes in the true ground plane (OV), which can affect the behavior of other components. The increase of the load capacitance, the decrease of the load resistance, the increase of the ground inductance, and the increase of the number of switching devices will all lead to the increase of the ground bounce. Due to the division of the ground plane (including power supply and ground), for example, the ground plane is divided into digital ground, analog ground, shield ground, etc., when the digital signal goes to the analog ground area, the ground plane return noise will be generated. Likewise, power planes may also be split into 2.5 V, 3.3 V, 5 V, etc. Therefore, in the multi-voltage PCB design, the bounce noise and return noise to the ground plane need special attention.
3. Signal integrity solutions
The signal integrity problem is not caused by a single factor, but caused by a combination of factors in the board-level design. The main signal integrity problems include reflection, ringing, ground bounce, crosstalk, etc. The following mainly introduces crosstalk and reflection.
3.1 Crosstalk Analysis
Crosstalk refers to the undesired voltage noise interference on adjacent transmission lines due to electromagnetic coupling when a signal propagates on a transmission line. Excessive crosstalk may cause false triggering of the circuit, resulting in the system not working properly. Since the size of crosstalk is inversely proportional to the line spacing, it is proportional to the parallel length of the line. Crosstalk varies with circuit load. For the same topology and wiring, the greater the load, the greater the crosstalk. Crosstalk is proportional to the signal frequency. In digital circuits, the edge change of the signal affects the crosstalk. The faster the edge changes, the greater the crosstalk.
According to the above characteristics of crosstalk, it can be summarized into the following methods to reduce crosstalk:
1) Reduce the transition rate of the signal edge if possible. When selecting devices, try to choose slow devices while meeting design specifications, and avoid mixing different types of signals, because fast-changing signals have potential crosstalk danger to slow-changing signals.
2) The crosstalk generated by capacitive coupling and inductive coupling increases with the increase of the load impedance of the interfered line, so reducing the load can reduce the influence of coupling interference.
3) When the wiring conditions permit, try to reduce the parallel length between adjacent transmission lines or increase the distance between the capacitive coupling wires that may occur, such as using the 3W principle (the distance between traces must be a single trace width) 3 times or the distance between two traces must be greater than 2 times the width of a single trace). A more effective approach is to isolate the conductors with a ground wire.
4) Inserting a ground wire between adjacent signal wires can also effectively reduce capacitive crosstalk. This ground wire needs to be connected to the ground layer every 1/4 wavelength.
5) It is difficult to suppress inductive coupling. It is necessary to reduce the number of loops as much as possible, reduce the loop area, and avoid sharing the same section of wire for signal loops.
6) The signal layer traces of two adjacent layers should be vertical, and parallel traces should be avoided as much as possible to reduce crosstalk between layers.
7) The surface layer has only one reference layer, and the coupling of the surface layer wiring is stronger than that of the middle layer. Therefore, the signals that are more sensitive to crosstalk should be placed in the inner layer as much as possible.
8) Through termination, the far and near ends of the transmission line and the terminal impedance are matched with the transmission line, which can greatly reduce crosstalk and reflection interference.
3.2 Reflection Analysis
When the signal propagates on the transmission line, as long as the impedance change is encountered, reflection will occur. The main method to solve the reflection problem is to perform terminal impedance matching.
1) Typical Transmission Line Termination Strategy
In high-speed digital systems, the impedance mismatch on the transmission line will cause signal reflection. The method to reduce and eliminate the reflection is to perform terminal impedance matching at the transmitting end or the receiving end according to the characteristic impedance of the transmission line, so that the source reflection coefficient or load reflection coefficient is O. The length of the transmission line meets the following conditions and should use termination technology: L>tr/2tpd. In the formula, L is the length of the transmission line; tr is the rise time of the source signal; tpd is the load transmission delay per unit length of the transmission line. Two strategies are usually adopted for the termination of transmission lines: matching the load impedance with the impedance of the transmission line, that is, parallel termination; and matching the source impedance with the impedance of the transmission line, that is, serial termination.
2) Parallel termination
Parallel termination is mainly to connect the pull-up or pull-down impedance as close to the load end as possible to achieve impedance matching of the terminal.
3) Serial termination
Serial termination is achieved by inserting a resistor into the transmission line in series as close to the source as possible. Serial termination is to match the impedance of the signal source. The resistance of the inserted serial resistor plus the output impedance of the drive source should be Greater than or equal to the transmission line impedance. This strategy suppresses the signal reflected back from the load by making the reflection coefficient at the source end (the load end inputs high impedance and does not absorb energy) and then reflects back from the source end to the load end.
3.2.2 Termination Technology of Different Process Devices
The technical solutions of impedance matching and termination vary with the interconnection length and the series of logic devices in the circuit. Only using the correct and appropriate termination method for specific situations can effectively reduce signal reflections. Generally speaking, for a CMOS process drive source, its output impedance value is relatively stable and close to the impedance value of the transmission line, so using serial termination technology for CMOS devices will achieve better results; while the TTL process drive source is in The output impedance is different when outputting a logic high and low level. At this time, using the parallel Thevenin termination scheme is a better strategy; ECL devices generally have very low output impedance, so it is the ECL circuit to use a pull-down termination resistor at the receiving end of the ECL circuit to absorb energy. Universal termination technology. Of course, the above method is not the same. Differences in specific circuits, the selection of network topology, and the number of loads at the receiving end are all factors that can affect the termination strategy. Therefore, when implementing the circuit termination scheme in high-speed circuits, it is necessary to consider the specific situation. to select the appropriate termination scheme to obtain the best termination effect.
4. Signal integrity analysis and modeling
Reasonable circuit modeling and simulation is a common solution to signal integrity. In high-speed circuit design, simulation analysis is increasingly showing its superiority. It provides designers with accurate and intuitive design results, which is convenient for early detection of problems and timely revisions, thereby shortening design time and reducing design costs. There are three commonly used models: SPICE model, IBIS model, Verilog-A model. SPICE is a powerful general-purpose analog circuit simulator. It consists of two parts: Model Equation and Model Parameters. Since the model equations are provided, the SPICE model can be closely connected with the simulator's algorithm, and better analysis efficiency and analysis results can be obtained; the IBIS model is specially used for digital signal integrity at the PCB board level and system level. Analytical model. It uses the form of I/V and V/T tables to describe the characteristics of digital integrated circuit I/O units and pins. The analysis of the IBIS model mainly depends on the number of data points and the degree of data in the 1/V and V/T tables. Compared with the SPICE model, the IBIS model is computationally small. To ensure that the
PCB board has good signal integrity, it is necessary to integrate a variety of influencing factors, rational layout and wiring, so as to improve product performance.
