PCB News - Comment on common problems of system efficiency in PCB design

Question 1: This CPU with a frequency of 100M can only handle 70%, and it will be fine if you change to a CPU with a frequency of 200M.

Comment: The processing capacity of the system involves a variety of factors. In the communication business, the bottleneck is generally in the memory. No matter how fast the CPU is, it is futile that external access can't get up.

Question 2: If the CPU uses a larger CACHE, it should be faster

Comment: The increase of CACHE does not necessarily lead to the improvement of system performance. In some cases, closing CACHE is faster than using CACHE. The reason is that the data moved to CACHE must be reused many times to improve system efficiency. Therefore, in the communication system, generally only the instruction CACHE is opened. Even if the data CACHE is opened, it is only limited to part of the storage space, such as the stack part. At the same time, the program design is also required to take into account the capacity and block size of the CACHE, which involves the length of the key code loop body and the jump range. If a loop is just a little bit larger than the CACHE, and the loop is repeated, it will be miserable.

Question 3: Do so many tasks use interrupts or queries? Or should they interrupt faster?

Comment: The interruption is real-time, but not necessarily fast. If there are too many interrupted tasks, this one does not exit, and then comes one after another, and the system will crash in a while. If the number of tasks is large but very frequent, a lot of the CPU energy is spent on the overhead of in and out of the interrupt, and the system efficiency is extremely low. If you switch to the query mode, the efficiency can be greatly improved, but the query sometimes cannot meet the real-time requirements, so The best way is to query in the interrupt, that is, after entering an interrupt, all the accumulated tasks will be processed and then exit.

Question 4: The timing of the memory interface is the factory default configuration, and there is no need to modify it

Comment: The default values of the BSP settings for the memory interface are all set according to the most conservative parameters. In actual applications, the bus operating frequency and waiting period should be combined with parameters for reasonable deployment. Sometimes reducing the frequency can improve efficiency. For example, when the RAM access cycle is 70ns and the bus frequency is 40M, set the access time of 3 cycles, that is, 75ns; if the bus frequency is 50M, it must be set to 4 Cycle, the actual access time has slowed down to 80ns.

Question 5: If one CPU can't handle it, just use two distributed processing, and the processing power can be doubled

Comment: For moving bricks, two people should be twice as efficient as one; for painting, one more person can only help. How many CPUs to use can only be determined after having more knowledge about the business. Try to reduce the cost of coordination between the two CPUs, and make 1+1 as close to 2 as possible, and never be less than 1.

Question 6: This CPU has a DMA module, it must be faster to use it to move data

Comment: The real DMA is to start both devices at the same time after the hardware preempts the bus, and read here and there in one cycle. However, many DMAs embedded in the CPU are just simulations. Before starting each DMA, a lot of preparatory work (set the starting address and length, etc.) must be done. During the transfer, the temporary storage in the chip is often read first, and then written out. That is to say, it takes two clock cycles to move the data once, which is faster than the software to move (no instruction fetching, no extra work such as loop jumps), but if you only move a few bytes at a time, you still need to do a lot of preparatory work. Generally, it also involves function calls, which is not efficient. Therefore, this DMA is only applicable to large data blocks.

The above is an introduction to the evaluation and analysis of common problems of system efficiency in PCB design. Ipcb is also provided to PCB manufacturers and PCB manufacturing t echnology.