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1 Introduction
2. Signal integrity issues
3. Electromagnetic compatibility issues
4. Power integrity issues
5. General specification for high frequency circuit design
6. General specification for design of digital-analog hybrid circuit

One: The definition of high frequency PCB
*In digital circuits, whether it is a high-frequency circuit depends on the rising and falling edges of the signal, not the frequency of the signal.
Formula: F2 =1/(Tr*π), Tr is the rise/fall delay time of the signal.

*F2> 100MHz, it should be considered in accordance with the high-frequency circuit, the following conditions must be designed in accordance with the high-frequency rules
-The system clock frequency exceeds 50MHz
-Using devices with rise/fall times less than 5ns
--Digital/analog hybrid circuit

*Logic device rise/fall time and wiring length limit rise/drop main harmonic spectrum distribution Maximum transmission line maximum transmission
Falling time Tr component F2=1/Fmax=10*distance (microstrip) line distance (microstrip line) πTr F2
74HC 13-15ns 24MHz 240 MHz 117cm 91cm
74LS 9.5ns 34 MHz 340MHz 85.5cm 66.5cm
74H 4-6ns 80 MHz 800MHz 35 28
74S 3-4ns 106 MHz 1.1GHz 27 21
74HCT 5-15ns 64 MHz 640MHz 45 34
74ALS 2-10ns 160 MHz 1.6GHz 18 13
74FCT 2-5ns 160 MHz 1.6GHz 18 13
74F 1.5ns 212 MHz 2.1GHz 12.5 10.5
ECL12K 1.5ns 212 MHz 2.1GHz 12.5 10.5
ECL100K 0.75ns 424 MHz 4.2GHz 6 5
Traditional PCB designmethods are inefficient:
Schematic diagram, traditional design method design and input layout and wiring do not have any quality control points. Every step of PCB design is based on experience. If problems are found, they must start from scratch. It is very difficult to find problems in functional and performance testing.

Signal integrity issues:
1. Reflection problem
2. Crosstalk issues
3. Overshoot and oscillation
4. Delay
Reflection problem: echo on the transmission line. Part of the signal power (voltage and current) is transmitted to the line and reaches the load, but there is a part
The points are reflected.
Multipoint reflection
Reason for reflection:
*Impedance mismatch between source and load
*The geometry of the wiring
*The direction of the wiring, via
*Incorrect wire termination
*Transmission through the connector
*Discontinuity of the power plane, etc.
Crosstalk issues:
*Crosstalk: Coupling between two signal lines
1. Capacitive crosstalk
*This happens when the lines are close to each other at a certain distance.
*Capacitive coupling induces coupling current
2. Inductive crosstalk
*Signal coupling between the primary coil and the secondary coil of the unneeded transformer
*Inductive coupling triggers coupling voltage.

Crosstalk issues:
The parameters of the PCB layer, the signal line spacing, the electrical characteristics of the driving end and the receiving end, and the line termination method all have a certain impact on the crosstalk.
*The crosstalk of capacitance and inductance increases with the increase of load impedance, so all lines susceptible to crosstalk should be terminated with line impedance.
Methods to reduce capacitive crosstalk:
* Separating signal lines can reduce the energy of capacitive coupling between signal lines.
*Using the ground wire to separate the signal line can reduce the coupling of capacitance. To improve effectiveness, the ground wire should be connected to the ground every λ/4 inches. (Λ wavelength refers to the distance the signal is transmitted per unit time.)
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General principles:
Punch holes every 2-5cm.
Simulation results of capacitive crosstalk
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Ways to reduce perceptual crosstalk
*In order to solve the crosstalk problem of inductance, the size of the loop should be reduced as much as possible.
*By avoiding the situation that the signal return line shares a common path, inductance crosstalk, overshoot and oscillation can also be reduced
*Overshoot: Overshoot can cause false clocks or bus data read/write errors.
*Ringing: The phenomenon of ringing is repeated overshoot and undershoot.
Signal oscillation and surrounding oscillation are caused by excessive inductance and capacitance on the line. The oscillation belongs to the under-damped state and the surrounding oscillation belongs to the over-damped state.
Oscillation can be reduced by proper termination, but it is impossible to completely eliminate it.
Time delay: the different time delays of each signal line in a set of buses
Clock and signal: ensure as wide a window as possible
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Electromagnetic compatibility issues
*Electromagnetic Interference (EMI) issues
1. Loop design, forming antenna effect
2. The slot in the power layer will form a quarter-wavelength antenna
*Dense vias (such as BGA packaged devices)
*Large connectors (especially the backplane)
3. Inductive components.
Note: Two parallel inductances on the component surface will form a transformer.
Unreasonable return path leads to EMI
EMI caused by incomplete ground plane
Incomplete ground plane can cause large EMI
The simulation without considering the incomplete ground plane is inaccurate
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Power integrity issues
*High-power high-speed devices: need a large transient current
*The ground layer and power layer are incomplete: 1. Split, via 2. Connector
*Filter capacitor: 3. Quantity, capacity, layout,
Selection of power supply filter capacitor:
The system has both high frequency noise and low C0G (non-ferromagnetic) type frequency noise. It is higher than other types by paralleling large electric 0.01μF capacitors.
Capacitance, small ESL device, extremely small 0.1μF capacitor, ESL device can expand the filtering range at high frequency and has better filtering performance
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Schematic design specification
Signal integrity and electromagnetic compatibility considerations
Correspondence between the schematic diagram and the PCB after the PCB is completed
General rules and requirements
*According to the unified requirements, select the drawing size, frame format, graphic symbols and text symbols in the circuit diagram.
* According to the electrical working principle of the product, the components should be arranged in a row or series from right to left and top to bottom.
*When the drawing is arranged, the power supply part is generally arranged at the bottom left, the input terminal is on the right, and the output is on the left.
*The working state of the movable components (such as relays) in the picture is in principle in the open and unpowered working position.
*Use all the power and ground pins of all chips.
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Signal integrity and electromagnetic compatibility considerations
*Add corresponding filtering/absorption devices to the input and output signals; add silicon transient voltage absorption diode or varistor SVC if necessary
*String resistors on the high-frequency signal output terminal.
*The decoupling capacitors in the high frequency area should be electrolytic capacitors or tantalum capacitors with low ESR
*When determining the value of the decoupling capacitor, select a capacitor with a smaller value under the condition of meeting the ripple requirements to increase its resonance frequency.
* The power supply of each chip must be added with decoupling capacitors, and the power supply of each module in the same chip must be separately added with decoupling capacitors; if it is high frequency, a magnetic bead/inductor must be added to the power supply side.