PCB News - [PCB design] Case sharing where DDR3 cannot run to the rated frequency

In some DDR3 series of articles, although there are a small part of the case that talks about the problem, it is only written to introduce the topic, and it is only to stop. Since it is a case, the ins and outs of the problem must be described clearly. The problem in this case is Such:

A customer has a board that needs to add some functions, and wants to change the original small board to a large board, but due to cost considerations, the original 8-layer board is changed to a 6-layer board. After the board is made, it will be DDR3 in the actual test. It can only work stably by down-clocking to 400MHz, while the previous 8-layer board can work stably at 533MHz. The power supply of the two versions is basically the same, and the model and batch of the main control and DDR3 chips are also the same. The customer is also more experienced. After many attempts such as adjusting the driver and ODT, they did not improve. Later, they found us.

Cause analysis: Everyone knows that the most direct influencing factor of the general DDR3 running below the rated frequency is the timing. Too small or insufficient timing margin will cause the system to work unstable or not run at all. The main factors affecting DDR3 timing are the following: power supply noise, crosstalk, equal length matching, signal quality, etc. As long as there are no problems with the above major points, there will be relatively fewer problems with DDR3 (provided that the hardware principle and software configuration are okay). Below we will tackle various factors individually. In this case, it is better to use the elimination method.

Power supply noise: The capacitance distribution is basically 0.1uF capacitors. There are no other capacitors. It is better to add a few large value capacitors at low frequencies. However, the test power supply noise is only about 20mV, which is relatively small, so The influence of power supply noise can be preliminarily eliminated.

Crosstalk problem: the data signal spacing is 10.55mil, the address signal is 10mil; the spacing between the signals is 2H(W), the line center distance is 3H(W), if space permits, the spacing can be increased appropriately.

•The average total length of the address signal is 2000mil minus a branch length of 400mil. It can be roughly known that the length of the master to one of the particles is 1600mil, and the shortest length of the data signal is only 550mil. The difference is relatively large, exceeding 1000mil.

This is also the biggest difference between the front and rear versions. Because the main control chip does not have a read-write balance function, and the previous 8-layer board is changed to a 6-layer board, the reduction of wiring space makes our engineers do not have to go too much. Winding, and the system cannot automatically adjust the deviation of the data and the clock, which ultimately leads to insufficient timing margin. This should be the main reason why DDR3 runs less than the rated frequency.