PCB News - DDR2 DDR3 PCB LAYOUT rules

Some netizens said that the DDR data line is latched by DQS, so the length should be kept equal. The address and control lines are latched by the clock, so they need to maintain a certain equal length relationship with the clock. Generally, there is no problem with equal length. In terms of impedance, generally speaking, DDR requires 60 ohms and DDR2 requires 50 ohms. Do not perforate traces to avoid discontinuity in impedance. In terms of crosstalk, as long as the line spacing is widened, one layer of signal is layered, and there is no problem. Some netizens also said that they simulated the results of DDR2: the clock-to-line length error is less than 0.5mm; the maximum length is less than 57mm; the length difference between the clock line and the relative address line is less than 10mm.

Nine Technology stated that whether it is using chips on the PCB board or using DIMM strips, DDR and DDRx (including DDR2, DDR4, etc.) are relatively difficult to read and write with traditional synchronous SDRAM. There are three main difficulties: first, timing. Because DDR uses double-edge triggering, and the general clock single-edge synchronization circuit, there is a big difference in timing calculations. The reason for the double-edge trigger of DDR is that the clock is multiplied inside the chip. It looks like the data address rate is the same as the clock to the outside. In order to ensure that a small phase difference skew of a group of signals can be judged, DDR uses packet synchronization to trigger the DQS signal on the data DQ signal, so the timing synchronization required on the DDR is between DQ and DQS, not between general data and clock. In addition, when testing the maximum and minimum flight time Tflight, the general signal is calculated between the signal edge passing the test level Vmeas and the low decision threshold Vinl and the high threshold Vinh. To ensure sufficient setup time and hold time, control The flight time does not take into account the speed of the signal itself. Because of the low level of DDR, only an intermediate level Vref is used as the test level. When calculating the setup time and hold time, the signal change edge rate slew rate must be considered, and additional extras must be added when calculating the setup time and hold time. The compensation of the slew rate. This compensation value is introduced in the DDR special specification or chip data. Second, match. DRR adopts SSTL level. This special buffer requires an external circuit to provide a pull-up. The value is 30-50 ohm, and the level VTT is half of the high level. This pull-up will provide the DC current for buffer operation, so the current is very large. In addition, in order to suppress reflections, transmission line impedance matching and series resistance matching are also required. The result of this is that on the DDR data signal, there is a series resistance of 10-22 ohm at each end, and a pull-up is close to the DDR end; for the address signal, a series resistance is connected to the transmitting end and a pull-up is close to the DDR end. Third, power integrity. Due to the small level swing of DDR (such as 2.5V for SSTL2 and 1.8V for SSTL1), it requires high reference voltage stability, especially Vref and VTT. The internal analog phase-locked loop is often used in the chip that provides the DDR clock. The reference power supply requirements are very high; because VTT provides large current, the power supply impedance is required to be low enough, and the power lead inductance is small enough; in addition, DDR synchronously works with many signals, high speed, serious synchronous switching noise, reasonable power distribution and good power supply The coupling circuit is very necessary.

1. CLK has the same length as X, and the difference between the longest and shortest is no more than 25mils

2. The length of DQS is Y, compared with CLK, Y should be in the range of [X-1500,X 1500mils]

3. The length of DM and DATA is Z, compare with the DQS of each group, Z should be in the interval of [Y-25,Y 25mils]

4. The length of A/C signal (control & command signal) is K, compare with CLK, K should be in the range of [X-1500,X 2000mils]

5. Impedance control: DQ DQS DM CONTROL COMMAND CLK impedance is 55ohm -15%

1. Wiring grouping
The memory in the ARM system is generally 32-bit or 16-bit, and is usually composed of one or two memory chips. The data lines can be divided into one group, two groups or four groups.
The division of a group is: DATA0-31, DQS0-3, DQM0-3 as a group;
Division of the two groups: DATA0-15, DQS0-1, DQM0-1 as a group, DATA16-31, DQS2-3, DQM2-3 as a group;
The four groups are divided into one group: DATA0-7, DQS0, DQM0 are one group, DATA8-15, DQS1, DQM1 are one group, DATA16-23, DQS2, DQM2 are one group, and DATA23-32, DQS3, DQM3 are one group.
It is divided into several groups, which can be determined according to the number of chips and the wiring density. When wiring, the signal lines of the same group must be on the same layer.
The rest are clock signals, address signals and other control signals. These signal lines are a group. This group of signal lines should be routed on the same layer as much as possible
2. Isometric matching
a. DATA0-31, DQS0-3, DQM0-3 of DDR are all matched with equal length, regardless of whether they are divided into one group, two groups or four groups. The error is controlled at 25mil. It can be longer than the address line, but not shorter.
b. The clock signal, address signal and other control signals are all matched with equal length, and the error is controlled at 50mil. In addition, if it is a DDR clock, it must be routed in accordance with the requirements of the differential line. The length of the two clock lines must be controlled within 2.5 mils of error, and the uncoupled length must be minimized. The clock line can be 20-50 mils longer than the address and other signal lines.
3. Spacing
The control of the spacing should consider the impedance requirement and the density of the trace. The usual spacing principle is 1W or 3W. If there is enough space for wiring, the data lines can be routed at a distance of 3W, which can reduce a lot of crosstalk. If it does not work, at least 1W spacing must be guaranteed. In addition, the distance between the data line and other signal lines must be at least 3W, and it is better if it can be larger. The distance between the clock and other signal lines should be kept at least 3W and as large as possible. 1W and 3W principles can also be adopted for the winding spacing, and the 3W principle should be used first.

The above is the introduction of DDR2 DDR3 PCB LAYOUT rules, Ipcb also provides PCB manufacturers and PCB manufacturing technology