PCB News - A hardware expert’s PCB design experience sharing

One: cost saving
Phenomenon 1: The resistance value of these pull-up/pull-down resistors does not matter much, so choose an integer 5K.
Comment: There is no resistance value of 5K in the market, the closest is 4.99K (accuracy 1%), followed by 5.1K (accuracy 5%), and its cost is 4 times and 2 times higher than that of 4.7K with an accuracy of 20%. . The resistance values of 20% precision resistors are only 1, 1.5, 2.2, 3.3, 4.7, 6.8 (including integer multiples of 10); similarly, 20% precision capacitors have only the above values. If you choose other types The value must use higher precision, and the cost will be doubled several times, but it will not bring any benefits.
Phenomenon 2: What color should the indicator light on the panel choose? I think blue is more special, so choose it
Comment: Other red, green, yellow, orange and other colors, regardless of size (under 5MM), have been mature for decades, and the price is generally below 50 cents, while blue is something that was invented in the past three or four years. Technology maturity and supply stability are both poor, but the price is four or five times more expensive. At present, the blue indicator light is only used in occasions that cannot be replaced by other colors, such as displaying video signals
Wait.
Phenomenon 3: This point of logic can also be built with a 74XX gate circuit, but it is too earthy, so use CPLD, which looks much more high-end
Comment: 74XX gate circuit is only a few cents, and CPLD is at least dozens of dollars, (GAL/PAL is only a few dollars, but the company does not recommend it). Not to mention the increase in cost by N times, it also adds several times of work to production and documentation.
Phenomenon 4: Our system requirements are so high, including MEM, CPU, FPGA and all chips must choose the fastest
Comment: Not every part of a high-speed system works at high speed, and every time the device speed increases by one level, the price almost doubles, and it also brings great negative effects to signal integrity problems.
Phenomenon 5: The PCB design requirements of this board are not high, just use a thinner wire and automatically arrange it.
Comment: Automatic wiring will inevitably take up a larger PCB board area, and at the same time it will produce many times more vias than manual wiring. In a large batch of products, the factors that PCB manufacturers consider for reducing prices are line width and overpass, in addition to business factors. The number of holes, which respectively affect the yield of PCB and the number of consumption of drill bits, saves the cost of the supplier, and finds a reason for the price reduction.
Phenomenon 6: As long as the program is stable, the code is longer, and lower efficiency is not the key
Comment: CPU speed and memory space are all bought with money. If you spend a few more days to improve the efficiency of the program when writing code, then the cost savings from reducing the CPU frequency and reducing the memory capacity are definitely worthwhile. The CPLD/FPGA design is similar.
Two: Low-power design
Phenomenon 1: Our system is powered by 220V, so we don’t need to care about power consumption.
Comment: The low-power design is not only for power saving, more benefits are that it reduces the cost of the power supply module and the cooling system, and reduces the interference of electromagnetic radiation and thermal noise due to the reduction of current. As the temperature of the equipment decreases, the life of the device is correspondingly extended (the operating temperature of a semiconductor device increases by 10 degrees, and the life is shortened by half)
Phenomenon 2: These bus signals are all pulled by resistors, so I feel more relieved
Comment: There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled. The pull-up and pull-down resistor pulls a simple input signal, and the current is less than tens of microamperes, but when a driven signal is pulled, the current will reach the milliamp level. The current system often has 32 bits of address data each, and there may be If the 244/245 isolated bus and other signals are pulled up, a few watts of power consumption will be consumed on these resistors (don't use the concept of 80 cents per kilowatt-hour to treat these few watts of power consumption).
Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Let it be empty first, I'll talk about it later
Comment: If the unused I/O port is left floating, it may become an input signal that repeatedly oscillates due to a little interference from the outside world, and the power consumption of MOS devices basically depends on the number of flips of the gate circuit. If it is pulled up, each pin will also have microampere current, so the best way is to set it as output (of course, no other signals with driving can be connected to the outside)
Phenomenon 4: There are so many doors left in this FPGA to use up, so you can play to your heart’s content
Comment: The power consumption of FGPA is directly proportional to the number of flip-flops used and the number of flips. Therefore, the power consumption of the same type of FPGA at different circuits and different times may differ by 100 times. Minimizing the number of flip-flops for high-speed flipping is the fundamental way to reduce FPGA power consumption.
Phenomenon 5: The power consumption of these small chips is very low, so there is no need to consider
Comment: It is difficult to determine the power consumption of the internal chip that is not too complicated. It is mainly determined by the current on the pin. An ABT16244 consumes less than 1 mA without load, but its indicator is each pin. It can drive a load of 60 mA (such as matching a resistance of tens of ohms), that is, the maximum power consumption of a full load can reach 60*16=960mA. Of course, only the power supply current is so large, and the heat falls on the load.
Phenomenon 6: The memory has so many control signals. My board only needs to use the OE and WE signals. The chip select should be grounded, so that the data comes out much faster during the read operation.
Comment: The power consumption of most memories when the chip selection is valid (regardless of OE and WE) will be more than 100 times larger than when the chip selection is invalid. Therefore, CS should be used to control the chip as much as possible, and as far as other requirements are met. It is possible to shorten the width of the chip select pulse.
Phenomenon 7: Why are these signals overshooting? As long as the match is good, it can be eliminated
Comment: Except for a few specific signals (such as 100BASE-T, CML), there is overshoot. As long as it is not very large, it does not necessarily need to be matched. Even if it is matched, it does not necessarily match the best. For example, the output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistance is used, the current will be very large, the power consumption will be unacceptable, and the signal amplitude will be too small to be used. Besides, the output impedance of a general signal when outputting a high level and outputting a low level is not the same, and there is no way to achieve a complete match. Therefore, the matching of TTL, LVDS, 422 and other signals can be acceptable as long as the overshoot is achieved.
Phenomenon 8: Reducing power consumption is a matter of hardware personnel, and has nothing to do with software
Comment: The hardware is just a stage, but the software is the performer. The access of almost every chip on the bus and the flip of every signal are almost controlled by the software. If the software can reduce the number of accesses to the external memory (using more register variables, More use of internal CACHE, etc.), timely response to interrupts (interrupts are often low-level active with pull-up resistors), and other specific measures for specific boards will make a great contribution to reducing power consumption.
Three: system efficiency
Phenomenon 1: This CPU with a main frequency of 100M can only handle 70%, and it will be fine if it is changed to a 200M frequency.
Comment: The processing capacity of the system involves a variety of factors. In the communication business, the bottleneck is generally in the memory. No matter how fast the CPU is, it is futile that external access cannot be fast.
Phenomenon 2: CPU with a larger CACHE, it should be faster
Comment: The increase of CACHE does not necessarily lead to the improvement of system performance. In some cases, closing CACHE is faster than using CACHE. The reason is that the data moved to CACHE must be reused many times to improve system efficiency. Therefore, in the communication system, generally only the instruction CACHE is opened. Even if the data CACHE is opened, it is only limited to part of the storage space, such as the stack part. At the same time, the program design is also required to take into account the capacity and block size of the CACHE, which involves the length of the key code loop body and the jump range. If a loop is just a little bit larger than the CACHE, and the loop is repeated, it will be miserable.
Phenomenon 3: Do so many tasks use interrupts or queries? Stop it faster
Comment: The real-time interruption is strong, but not necessarily fast. If there are too many interrupted tasks, this one does not exit, and then comes one after another, and the system will crash in a while. If the number of tasks is large but very frequent, a lot of the CPU energy is spent on the overhead of in and out of the interrupt, and the system efficiency is extremely low. If you switch to the query mode, the efficiency can be greatly improved, but the query sometimes cannot meet the real-time requirements, so The best way is to query in the interrupt, that is, after entering an interrupt, all the accumulated tasks will be processed and then exit.
Phenomenon 4: The timing of the memory interface is the factory default configuration, no need to modify
Comment: The default values set by the BSP for the memory interface are all set according to the most conservative parameters. In actual applications, the bus operating frequency and waiting period should be combined with parameters for reasonable adjustment. Sometimes reducing the frequency can improve efficiency. For example, when the RAM access cycle is 70ns and the bus frequency is 40M, set the access time of 3 cycles, that is, 75ns; if the bus frequency is 50M, it must be set to 4 Cycle, the actual access time has slowed down to 80ns.
Phenomenon 5: If one CPU can't handle it, just use two distributed processing, and the processing capacity can be doubled
Comment: For moving bricks, two people should be twice as efficient as one; for painting, one more person can only help. How many CPUs to use can only be determined after having more knowledge about the business. Try to reduce the cost of coordination between the two CPUs, and make 1+1 as close to 2 as possible, and never be less than 1.
Phenomenon 6: This CPU has a DMA module, it must be fast to move data
Comment: The real DMA is to start both devices at the same time after the hardware preempts the bus, and read here and there in one cycle. However, many DMAs embedded in the CPU are just simulations. Before starting each DMA, a lot of preparatory work (setting the starting address and length, etc.) must be done. During the transfer, the temporary storage in the chip is often read first, and then written out. That is to say, it takes two clock cycles to move the data once, which is faster than the software to move (no instruction fetching, no extra work such as loop jumps), but if you only move a few bytes at a time, you still need to do a lot of preparatory work. Generally, it also involves function calls, which is not efficient. Therefore, this DMA is only applicable to large data blocks.