PCB News - The influence of the development trend of the electronics industry on the circuit board

The influence of the development trend of the electronics industry on the circuit board

Trends and developments in assembly

The multi-function, high transmission speed, and miniaturization of portable electronic products are the biggest driving force for the continuous improvement of overall semiconductors, packaging, assembly, and PCBA boards. The following is an analysis of the development trend of each level of construction in the next 5 years.

1 Motivation for change
Due to the need for rapid product revolution and market innovation, the design of portable electronic products has developed some trend features, including miniaturization, light weight, less energy consumption, increased functions, advanced interfaces, wireless connections, fashionable styles, and more. Meet the needs of green environmental protection. The characteristics of the market are the shortened product life cycle, the integration of 3C applications, larger production, faster and real-time market response, and increased product complexity and diversity. In order to keep up with these, it is necessary to change the process of electronic packaging and assembly. An overview of the latest trends, their transitions, and their challenges; the trends of individual components, carrier boards, and assembly will be glimpsed from the following.

Generally speaking, maximizing the pin count and package size can accommodate more I/Os in a small amount. In order to limit the increase in package size, the pitch must be reduced to 0.3mm-depending on the price of BGA and CSP development. Under the same surface area, BGA and CSP packages can accommodate more I/Os and also have wider bumps^3 pitch. In the future, the prices of BGA and CSP will drop further, which will replace many QFP packaging markets. It is especially worth noting that Seated hcight (the distance from the top of the package to the PCB surface) will be reduced.

Two BGA package
By 2006, the number of I/Os will increase to 1200, which is a certain trend in the application of portable computers. In order to limit the size of the main body and avoid reliability problems, the surface configuration of the bumps will be developed towards a full-area-array type. For the same reason, the bump pitch will be slightly reduced. Seated height will be reduced to install a thinner final product. The most important BGA development trends are shown in Table 9.2.

Three Chip-Scale Packages (CSPs)
CSPs have two types of external pins, one is bump (BGA type), the other is solder pad (LGA type). The highest seated hight of LGA is lower because of its lack of bumps. Therefore, LGA has become more popular, although the lower stand-off height will reduce the lifetime of the second-level interconnect. The common development of the two package types is that the highest seated height will decrease and the number of I/Os will increase. The size of the package is reduced to 0.3mm due to the pitch of the buinp/land array, which will also be reduced. The size of bump/land will also be reduced. Table 1 shows the most important CSP trends.

A special form of CSPs is wafer-level CSPs (wafer-level CSPs), which are packaging types that are carried out before the wafer is cut into dies. The main advantage is that the cost of these packages is low, because the production unit is a wafer rather than a die, and the increase in wafer size is also conducive to the reduction of the cost of this package type.

Four Flip chip on board
In the field of portable consumer products, the number of I/Os directly bonded to the motherboard in the FC type has increased slightly, and the size of the die has not changed much. 1C technology can make higher-density circuits. Under the same size, the die can have More features.

Because the signal enhancement process on the chip has little effect on the number of I/Os. Both the die thickness and the bump pitch will be reduced. The minimum bump pitch varies depending on the connection technology used, which will be discussed later. The additional underfill process to ensure its reliability hinders the direct application of FC on the motherboard. Once the alternative technology matures, the application of FC will increase substantially. Possible alternatives are Iio-flow primer (a mixture of high-viscosity flux and primer) and back-sealing glue on the wafer.

Five comparison of various 1C package types
Table 3 is a comparison of the above-mentioned different package types. From QFP, BGA, CSP to WL-CSP, the density of Flip-Chip and I/O has increased, while the pitch and package size have shrunk. The electrical and thermal properties have improved, but the heavy-duty capability, workability, electrical testing, degree of crystal grain protection, compatibility with 1C design and standard reflow, and component universality have become poor. In terms of reliability, QFPs and FCs provide the best results. QFP, WL-CSP and FLIP-CHIP have cost advantages, especially QFP is the lowest.

Six passive components passive components
It can be expected that by 2006, the size of capacitors and resistors will be reduced to 0101 size. The so-called integrated passive component refers to the integration of several passive functions in a silicon or ceramic die (I/O number> 2). Some passive components are also integrated into silicon 1C (such as decoupling capacitors).

Multi-layer carrier boards (ceramic or organic) are used in mold resistance assembly, and some specific passive functions are integrated into it.