PCB News - Protel to Allegro /CCT format conversion for PCB proofing

The development of PCB proofing today's IT industry is changing with each passing day, and the requirements for hardware equipment are getting higher and higher. Hardware designers are facing the problem of how to design high-speed and high-density PCBs. As the saying goes, if workers want to do their jobs well, they must first sharpen their tools. This is why more and more designers abandon low-end PCB design tools and choose high-performance PCB EDA software provided by companies such as Cadence.

The change of PCB proofing will inevitably bring about problems of one kind or another. Due to early contact and use, there are a large number of Protel users in China. When they choose Cadence high-speed PCB solutions, they all face the problem of how to transplant their Protel designs into Cadence PCB design software.

The problems encountered by PCB proofing in this process can be roughly divided into two types: one is that the design is not very complicated, and the designer only wants to use the powerful automatic wiring function of Cadence CCT to complete the wiring work; the other is that the design is complex, and the designer needs to rely on trust Noise analysis tools are used to simulate the signal and noise of the design and set the wiring topology of the wire network.

For the first case, the conversion work to be done is relatively simple. You can use the Protel to CCT conversion tool provided by Protel or Cadence to complete this work. For the second case, the work to be done is relatively more complicated, and this transformation method will be briefly introduced below.

The analysis object of the Cadence signal-to-noise analysis tool for PCB proofing is the brd file of Cadence Allegro, and Allegro can read third-party netlists that meet its requirements. The Telexis format netlist output by Protel meets Allegro's requirements for third-party netlists. You can inject Protel files into Allegro.

Here are two points for the reader's attention. First, Allegro third-party netlists do not allow "." in the $PACKAGE section; second, in Protel, we use the form of BasName[0:N] to represent the bus, and BasName[x] to represent a signal in the bus. The representation of a signal in the bus in the Allegro third-party netlist is Bas NameX. Readers can solve these problems by directly modifying the Telexis netlist output by Protel.

Allegro also needs the device description file Device.txt file of each type of device when injecting the third-party netlist. Its format is as follows:

Package: package type

Class: classtype

Pincount: total pinnumber

Pinused: ...

The commonly used items for PCB proofing are PACKAGE, CLASS, and PINCOUNT. PACKAGE describes the package of the device, but Allegro will use the PACKAGE item in the netlist and ignore this item in the device description file when injecting the netlist. CLASS determines the type of the device for signal-to-noise analysis. Cadence divides the device into three categories: IC, IO, and DISCRETE. PINCOUNT indicates the number of pins of the device. For most devices, it is sufficient to include these three items in the Device.txt file.

With a third-party netlist and device description file for PCB proofing, we can substitute the schematic design in Protel into the Cadence PCB design software in the form of a netlist. Then, the designer can use Cadence PCB software at high speed and high density. The powerful function of PCB design completes your own design.

PCB proofing If PCB layout work has been done in Protel, Allegro's script function can reproduce the layout in Protcl in Allegro. In Protel, designers can output a Place & Pick file, which contains the position, rotation angle and information of each device on the top or bottom of the PCB. You can easily generate an Allegro script file from this file., Executing this script in Allegro can reproduce the layout in Protel. The C++ code to complete the conversion of Place & Pick files to Allegro Script files is given below. The author uses this code and only takes a few minutes to transfer a user The PCB layout of more than 800 devices was reproduced in Allegro.

FILE *fp1, *fp2;

::AfxMessageBox("hello");

fp1=fopen("pick.txt", "rt");

if (fp1==NULL) ::AfxMessageBox("Can not open the file!!!");

fp2=fopen("place.txt","wt");

if (fp2==NULL) ::AfxMessageBox("Can not create the file!!!");

char refdes[5], Pattern[5];

float midx,midy,refx,refy,padx,pady,rotation;

char tb[1];

char tmp='"';

fprintf(fp2,"%s\n", "# Allegro script");

fprintf(fp2,"%s\n", "version 13.6");

fprintf(fp2,"%s\n", "place refdes");

while (!feof(fp1)) {

fscanf(fp1,"%s", refdes);

fscanf(fp1,"%s", Pattern);

fscanf(fp1,"%f", &midx);

fscanf(fp1,"%f", &midy);

fscanf(fp1,"%f", &refx);

fscanf(fp1,"%f", &refy);

fscanf(fp1,"%f", &padx);

fscanf(fp1,"%f", &pady);

fscanf(fp1,"%s", tb);

fscanf(fp1,"%f", &rotation);

fprintf(fp2, "fillin %c%s%c \n",tmp,refdes,tmp);

if (rotation!=0) {

fprintf(fp2, "rotate\n");

fprintf(fp2, "iangle %f\n", rotation);

};

char yy=tb[0];

if (yy!='T') fprintf(fp2, "pop mirror\n");

fprintf(fp2, "pick %f %f \n", padx,pady);

fprintf(fp2, "next \n");

};

fprintf(fp2, "done");

fclose(fp1);

fclose(fp2);

The above briefly introduces the conversion method of Protel to Allegro, and I hope it can be helpful to readers' design work.