IC Substrate - Application Analysis of IC Embedded Substrate Technology

1.BGA (ball grid array) ball contact display, one of the surface mount packages. On the back of the printed circuit board, spherical bumps are produced in the display mode to replace the pins, and the LSI chip is assembled on the front side of the printed circuit board, and then sealed by molding resin or potting. Also known as bump display carrier (PAC). Pins can exceed 200, which is a package for multi-pin LSI. The package body can also be made smaller than QFP (Quad Flat Package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; while a 304-pin QFP with a pin center distance of 0.5mm is 40mm square. And BGA does not have to worry about pin deformation problems like QFP. This package was developed by Motorola Corporation of the United States. It was first used in portable phones and other devices, and it may be popularized in personal computers in the United States in the future. Initially, the BGA pin (bump) center distance was 1.5mm, and the number of pins was 225. There are also some LSI manufacturers that are developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not yet clear whether an effective visual inspection method is available. Some believe that due to the large welding center distance, the connection can be regarded as stable and can only be handled through functional inspection. American Motorola Company calls the package sealed with molded resin OMPAC, and the package sealed with potting method is called GPAC (see OMPAC andGPAC).

2. BQFP (quad flat package with bumper) quad flat package with bumper. One of the QFP packages, bumps (buffer pads) are provided at the four corners of the package body to prevent bending and deformation of the pins during transportation. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The pin center distance is 0.635mm, and the pin number is about 84 to 196 (see QFP).

3. Butt joint PGA (butt joint pin grid array) Another name for surface mount PGA (see surface mount PGA).

4. C-(ceramic) represents the mark of ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.

5. Cerdip uses glass-sealed ceramic dual-in-line package for ECL RAM, DSP (digital signal processor) and other circuits. Cerdip with glass window is used for ultraviolet erasable EPROM and microcomputer circuit with EPROM inside. The pin center distance is 2.54mm, and the number of pins ranges from 8 to 42. In Japan, this package is expressed as DIP-G (G means glass seal).

6. Cerquad is one of the surface mount packages, which is a ceramic QFP sealed underneath, which is used to package logic LSI circuits such as DSP. Cerquad with windows is used to encapsulate EPROM circuits. The heat dissipation is better than that of plastic QFP, and it can tolerate 1.5~2W power under natural air cooling conditions. But the packaging cost is 3 to 5 times higher than that of plastic QFP. The pin center distance has a variety of specifications such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and so on. The number of pins ranges from 32 to 368.

7. CLCC (ceramic leaded chip carrier) is a leaded ceramic chip carrier, one of the surface mount packages. The leads are drawn from the four sides of the package and are in a T-shape. It is used to encapsulate the ultraviolet erasable EPROM and the microcomputer circuit with EPROM with windows. This package is also called QFJ, QFJ-G (see QFJ).

8. COB (chip on board) chip on board packaging is one of the bare chip mounting technologies. The semiconductor chip is handed over and mounted on the printed circuit board. The electrical connection between the chip and the substrate is realized by wire stitching. The electrical connection between the chip and the substrate The connection is made by wire stitching and covered with resin to ensure reliability. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip bonding technology.

9. DFP (dual flat package) dual flat package. It is another name for SOP (see SOP). There used to be this term, but it is basically not used now.

10.DIC (dual in-line ceramic package) Another name for ceramic DIP (including glass seal) (see DIP).

11. DIL (dual in-line) Another name for DIP (see DIP). European semiconductor manufacturers often use this name.

12. DIP (dual in-line package) dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic ICs, memory LSIs, and microcomputer circuits. The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow DIP) respectively. However, in most cases, there is no distinction, and they are simply collectively referred to as DIP. In addition, ceramic DIP sealed with low-melting glass is also called cerdip (see cerdip).

13. DSO (dual small out-lint) dual small out-lint package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.

14. DICP (dual tape carrier package) dual tape carrier package. One of TCP (Tape Carrier Package). The pins are made on the insulating tape and lead out from both sides of the package. Due to the use of TAB (Automatic On-Load Soldering) technology, the package outline is very thin. It is often used in LCD driver LSIs, but most of them are custom products. In addition, the 0.5mm thick memory LSI thin package is in the development stage. In Japan, in accordance with EIAJ (Electronic Machinery Industry of Japan) Association standards, DICP is named DTP.

15. DIP (dual tape carrier package) Same as above. The Japanese Electronic Machinery Industry Association standard names DTCP (see DTCP).