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Heterogeneous 3DIC still faces mass production threshold
Although the 3DIC+TSV three-dimensional stacking technology can increase the density of the chip with the smallest area, reduce costs and reduce the product size, and thus improve the performance and reliability of the chip, Samsung is also the first to introduce a homogeneous 3DIC stacked NANDFlash flash Memory, DDR3 memory, and stacked WideI/ODRAM chips for desktop and notebook computers.IC design companies such as Qualcomm and BroadComm have also introduced 3DTSV technology to design next-generation higher-density ICs.
2.5D technology has been widely applied to logic operation chips such as CPU/GPU/FPGA. IBM/AMD 2.5D/3DIC technology will further drive heterogeneous integration applications such as DRAM, CIS, RF, LED, and optoelectronic components. Yole International Semiconductor Association (SEMI) continues to carry out the 3DTSV plan, and invites HP, IBM, Intel, Samsung, Qualcomm, TSMC, UMC, Hynix, Atotech, ( ASE, ST, Samsung, Micron, GlobalFoundries, NEXX, FRMC and other industries have actively invested in 3DIC R&D and production, and built a 3D industry chain ecology with clear specifications.
The current integrated application of 3DIC still belongs to the same manufacturing process, homogeneous chip (Homogenuous) integration, such as DRAM, NANDFlash die, or multi-core microprocessor. IEK expects that from this year (2013), 3DIC such as DRAM and NANDFlash with homogeneous stacking is expected to enter mass production. As for the heterogeneous integration of logic chips (Logic), memory chips (DRAM), radio frequency ICs (RF), power amplifiers (PA), photoelectric conversion chips, etc., it is limited by technical issues such as power consumption and packaging material coefficients. It has yet to be overcome.
2.5D intermediary technology is the first to introduce FPGA, GPU/APU into mass production
As mentioned earlier, 3DIC is used in Hetergeneous Integrated. It stacks up bare silicon chips with different logic processes and operating characteristics, and uses TSV (Silicon Drilling) technology to interconnect the chips. When different types of chips are stacked, power consumption and heat dissipation issues will require special treatment.
If only a DRAM chip with 1V voltage and 2W power consumption is stacked, the startup current is about two amperes. If a 2GHz, multi-core processor CPU or graphics processing unit (GPU) is stacked on it, it will easily require tens of watts or even more. One hundred watts, the light-starting current may be as high as tens of amperes, which can almost be dealt with by car-grade batteries. This kind of chip is fatal for the design of mobile portable devices; and it supplies large current in such a limited and dense area. The wiring design of the power supply circuit and the selection of power chips are technical challenges, and even the current itself is the biggest source of interference that affects the efficiency and stability of the circuit.
High-frequency operation CPU and GPU chips can usually heat up to 120 degrees. However, when the DRAM and NANDFlash die exceed 85°C, the refresh mechanism and storage tolerance will be abnormal. If the CPU is combined with DRAM, NANDFlash Stacked together, the high heat of the CPU will affect DRAM and NANDFlash; in addition, like photoelectric conversion devices, the operation stability will be greatly reduced when the temperature reaches 80°C or more. There are also different types of bare die materials. When stacked together, the thermal stress effect on the packaging mechanism caused by different thermal expansion coefficients must be considered, and even overheating will cause the deformation of the stacked wafer layer and even the tin cracking. How to properly arrange the stacking sequence of these chips with different temperature characteristics so that they will not affect each other during heat dissipation is a very severe technical challenge. This is the reason why 3DIC, which has been mass-produced, appears first in low-power DRAM and NANDFlash-equivalent stacked products.
2.5DIC (or 2.5DInterposer) technology was first proposed by the factory leader (ASE), and later became a term followed by the semiconductor industry. The method is to make the dies of various processes/working characteristics not stacked on each other, but arranged in parallel and close to each other, placed on the glass or silicon-based material Interposer (interposer) for connection, and then connected to the bottom The PCB circuit board shortens the signal delay time and improves the overall system performance; each parallel die can be individually tested and then perforated and assembled side by side. It does not need to go through the heat/electromagnetic radiation test, as long as it is placed on the intermediate board ( Interposer) can go through an overall integration test after packaging. When performing 3DIC stacking, thermal/electromagnetic testing must be performed on each layer in the stack; if one of the die is defective, the entire 3DIC stacking device must be reimbursed.
2.5DIC is regarded by the semiconductor industry as an intermediary technology for the transition to the future 3DIC. In addition to using Interposer to act as a communication bridge between chips, attention must also be paid to issues such as the combination of die and Interposer, material properties, and thermal stress. Compared with 3DIC, 2.5DIC has a lower technical bottleneck. The silicon interposer used in the circuit board (SIInterposer) generally does not need to use the 40nm or even 28nm advanced manufacturing process like the processor chip, and the manufacturing cost can be reduced.
Take Xilinx2.5D FPGA processor chip as an example. After the bare 28/40nm FPGA chips are arranged side by side, they are placed on a 65nm silicon interposer. The total cost is lower than the previous 40nm or even 28nm SOC process. Therefore, the application field of 2.5DIC is not limited to memory chips. High-performance and highly integrated logic computing chips such as FPGA, CPU, GPU, etc., have begun to apply 2.5DInterposer technology.
2.5D/3DIC killer application
Semiconductors who have introduced the 2.5DIC concept into mass production are represented by the leading programmable logic gate array (FPGA) manufacturers Xilinx and Altera. Both companies use TSMC's CoWos (ChiponWaferonSubstrate) 2.5DIC technology. Like Xilinx’s Virtex-72000TFPGA chips, 28nm bare dies are closely arranged side by side. The micro bumps under the bare dies are connected to a 65nm silicon interposer. After that, they are connected to the solder balls by TSV technology and then penetrated. Connect the solder ball to the PCB board below.
In addition, the IntelIrisPro5200 (GT3e) graphics chip matched with the IBM Power8 processor, Intel’s fourth-generation Corei processor (Haswell), and AMD’s semi-customized 8 The core APU will also use 2.5DIC packaging technology.
As for the 3DIC part, in addition to the homogeneous stacking of DRAM chips (WideI/O) and NANDFlash chips, Altera recently announced the next-generation 20nm FPGA products, which will use TSMC’s next-generation 20nm process plus 3DIC heterogeneous integration and stacking technology. Integrating more than two sets of FPGA die, ARM multi-core processor chip, user-customizable HardCopyASIC chip, adjustable precision DSP digital signal processor, and multi-layer stacked MemoryCube memory chip.
ASE, Silicon Products, Licheng and Nanmao have a share of 56% of the global packaging and testing foundry market, which is also the key to the last mile in the 3DIC industry chain. ASE adopts the 3DS-IC standard of the SEMI specification platform, and actively cooperates with DesignHouse and Foundry to complete the DietoDie, DietoSiP overlay interconnection specifications, and 3D stacking, measurement and packaging reliability confirmation; in Foundry, Memoryhouse and packaging and testing 3D carrier boards, fixtures, holding procedures between factories, as well as participation in TSV wafers, JEDECJC-11WideI/O memory stacking methods, and 3DQA quality assurance related specifications.
In addition, TSMC has also introduced 2.5D/3DIC structure CoWoS (ChiponWaferonSubstrate) integrated production technology, providing TSV/3D, various bumping materials including ball planting technology, silicon interposer (Si-Interposer) and various sub-system integration, etc. One-stop shopping service. At the same time, continue to invest in 2.5D/3DIC technology to accelerate the introduction of the entire industry chain of EDA, IP, testing, equipment, silicon wafer suppliers and packaging plants. UMC and downstream packaging and testing plants are looking for an open industry model (OpenEcosystemModel) to develop 3DIC technology.
IEK pointed out that 3DIC technology has been introduced into memory storage chips such as NANDFlash and DRAM before 2010. Since 2010, mass production of CIS (CMOS image sensor) and MEMS (microelectromechanical) components has also been introduced. There are applications such as power amplifier chip (PA), LED lighting chip packaging, and photoelectric conversion element packaging. In 2013, it is expected that the homogeneous multi-layered MemoryCube and WideI/ODRAM will be mass-produced; and the heterogeneous 3DIC (Heterogeneous 3DIC) integrating multi-core CPU, FPGA, ASIC, memory, and optoelectronic components is expected to be introduced between 2014 and 2015 Actual mass production stage.
