PCB Technical - Focus on signal integrity in complex designs

Abstract: In SoC design, the coupling between signals will cause signal integrity problems. Ignoring the signal integrity problems may lead to crosstalk between signals, and reliability, manufacturability and system performance will also be reduced. This article describes in ASIC The method to solve the signal integrity problem in the chip design.

For the design of ASIC (application specific integrated circuit), due to the application of standard cells, shorter development cycles, and looser protection zones between the cells, the performance of the standard cells is wasted. Therefore, the key to high-end ASIC chip design is to ensure that high-performance chips are delivered in a short development time.

With the development of process technology, the chance of causing signal crosstalk has increased. The number of metal wiring layers continues to increase: from 4 or 5 layers in the 0.35um process to more than 7 metal wiring layers in the 0.13um process. As the number of wiring layers increases, the adjacent channel capacitance will also increase. In addition, the rapid increase in the number of circuit gates in current complex designs necessitates more and longer interconnect lines. The resistance on the long wires will increase, and thinner and thinner metal wires will also increase the resistance due to the decrease in the cross-section of the interconnection wires. Even if the existing copper wire interconnection process is used, this problem cannot be solved, but it only delays the time to solve the resistance problem.

Obviously, the influence between these adjacent signal lines dominates design decisions and requires a different and more accurate model than in the past. The influence of one signal on another is related to the relative phase between the signals. For signals with the same phase, a victim network with a small receiver and transmitter connected to a 0.5mm long signal line will be accelerated by 30%. For 1mm long signal lines, the victim network will be accelerated by 40%. For signals with opposite phases, a victim network with a small receiver and transmitter connected to a 0.5mm long signal line will decelerate by 70%. When the signal line length is 1mm, the signal will decelerate by more than 100%.

One way to solve the signal crosstalk problem is to increase the spacing between metal signal lines. By doubling the signal line spacing, the signal crosstalk on the 0.5mm signal line can be reduced from 70% to 20%. The interference on long signal lines (1mm signal lines) will also be reduced from 100% to 40%. However, the crosstalk between the signals still exists, and the method of reducing the crosstalk between the signals by doubling the metal line spacing will increase the chip area and increase the difficulty of wiring.

Take shielding measures

Another way to solve the above problems is to take shielding measures. Add power or ground wires on both sides of the signal wire, and signal crosstalk will be greatly reduced. Adding shielding measures to the system also requires that all components have a good bypass, and at the same time, it should be ensured that the power supply and ground should be as "clean" as possible. In fact, from an area point of view, this solution is worse than the method of doubling the metal line spacing. This is because in this case the signal line spacing is 4 times the minimum line spacing, so this kind of ground The method of line spacing will increase the complexity of wiring by an order of magnitude.

However, the shielding method may be more suitable for some signal lines. For example, the clock line has a very high speed and the largest drivers and buffers are connected to such signal lines. Phase-locked loop technology can compensate for the additional signal delay on the driver and buffer. Proper layout ensures that an isolated environment is formed around the clock signal, thereby minimizing the interference of the clock signal to the data signal.

In this method, design engineers use extraction and analysis tools to detect areas that are prone to signal integrity problems, and then select some of them and solve the problems in this area. If the problematic signal lines are isolated from each other, rewiring can solve the problem. The simpler approach is to change the size of the drive and add a buffer to the victim network.

The logic synthesis process always selects the appropriate driver based on the approximate estimated value of the online load. Generally speaking, logic synthesis always chooses a stronger driver to achieve over-compensation of the expected load. However, the load is actually unknown before the physical design is completed, and the actual load may vary from -70% to +200% compared to the expected load situation. The worst case may be that a short-term driver with too large a load is followed by a lightly-loaded long-term driver. One solution to the driver problem is to use a buffer to divide long lines. This can reduce the length of the line and the coupling capacitance, and it can also reduce the load on the input of the buffer to the level of a single load. This technology ensures that minor changes are made in the buffer placement and routing process to ensure the implementation of bottom-level planning and optimization. Adding a static timing analysis step to the design flow can handle noise and delay issues. The purpose of this is to integrate the steps to solve crosstalk and timing into one flow. First, these tools extract the parasitic parameters after placement and routing. Secondly, according to the extracted load model, the signal delay is calculated without considering any crosstalk effects. These extracted delays are then marked in the design and static timing analysis tools are used to determine incorrect timing. After getting the first approximation of the timing window, the design engineer adds the delay due to crosstalk and checks whether the timing will exceed the assigned timing window. The complete design flow requires three static timing analyses.

Reliability and manufacturability

The trend in the industry today is that the number of chip gates continues to increase, and the performance of the chip is also improved as the feature size shrinks. Moore's theorem states that the clock speed and the number of circuit gates double every 18 months. In order to maintain the safe working limit in the design, the continuous refinement of process technology requires that the power supply voltage must be reduced accordingly. At the same time, the power consumption on each circuit gate is also decreasing. The decrease in power supply voltage and the decrease in power consumption on each gate always fail to keep up with the increase in the number of gates and the increase in clock frequency.

For example, in a new generation of process technology, a high-performance processor has a planned power consumption of 300W under the condition of a 1.8V power supply voltage. The average size of ASIC chips will reach 34 million gates, and the clock frequency will exceed 450MHz. The power supply current of next-generation ASIC chips will be much higher than that of existing chips. Compared with the same ASIC design in the 0.35um process, the power consumption of the 0.18um ASIC chip will exceed 6 times, and the current intensity will exceed 10 times.

The increase in power consumption and current will cause the migration of electrons. There will be metal migration on high-power unidirectional networks due to the flow of current, especially when the current flows through the bend of the signal line or into a small space. The self-heating phenomenon at the high resistance of the signal line through which the bidirectional current flows can also cause migration problems.

The shrinking of the chip feature size also requires a corresponding reduction in the size of the gate oxide region. The high potential region in the switching circuit can trap electrons in the gate oxide region. The destruction of the oxidation zone and the resulting change in the corresponding gate threshold is a cumulative process, which is related to the switching frequency and depends on the signal conversion rate.

If the switching frequency is maintained below a safe limit, the normal operating life of the device can be predicted. However, the challenge is to develop a new method to control the thermal electron effect corresponding to the frequency or conversion rate above the safety limit. The user must fully characterize these effects. First, they must simulate the transient conditions of the internal standard cell circuit. Then they must compare the simulation results under the current density limitation with the test results of the actual silicon wafer structure. Finally, they need to create a device model that accurately reflects the actual device and process technology.

Circuit analysis follows a number of different methods, and all of these methods require the calculation of the actual switching frequency. One way to solve the problem is to simulate the accurate response of all circuits based on the characteristic model. Another approach is to develop a probabilistic model to closely approximate the actual behavior in the silicon structure.

To solve the problems related to metal migration and hot electron injection, the first method is to insert buffers on long wires, which usually have higher currents and faster signal switching speeds. It should be emphasized that if the buffer speed is just lower than the driver, this method can reduce the load capacitance on the signal line and reduce the signal conversion rate. Another possible solution is to change the driver and receiver units.

Antenna effect and noise

The plasma etching process on the metal layer forces the charge to accumulate on the gate of the IC. The ratio of the smaller and smaller gate area to the ever-increasing length of the interconnection signal line will result in capacitive partial pressure, which will further damage the device, which is a cumulative process. The basic method to minimize this antenna effect is to limit the ratio of the area of the metal area to the circumference, and limit the ratio of the area of the grid area to the circumference. Adopting such rules can reduce the process of charge accumulation and transfer.

Another alternative strategy is to use a wiring tool that relies on antenna compensation wiring rules. In this way, the antenna current can be prevented or minimized, but the cost of this method is that the chip area is larger. Another possible method is to connect a long antenna to the diffusion area, and use the diffusion resistance to transfer the charge to other areas (such as the substrate). Finally, inserting a buffer can also reduce the length of the line and insert a diffusion resistor (P-type or N-type output transistor channel) as a resistance path to the power supply or ground.

The increase in power consumption and power supply current will also bring other problems. Large currents will cause a voltage drop on the power supply line. Therefore, when the current flows through a non-zero resistance power supply network, an IR voltage drop will be generated, thus reducing the voltage reaching the gate. The method of reducing the resistance on the power supply network is restricted by chip area and wiring congestion. Extraction and analysis in the physical verification stage requires a complex, full-chip simulation and analysis process, which includes simulation and analysis of transient processes, inductance and capacitance effects.

However, after the placement and routing is completed, there is little or no possibility to solve the above-mentioned problems, so the situation will be worse. The best way to solve the problem of power consumption is to conduct serious research on design planning and implementation strategies in the early stages of design and even in the RTL design stage. RTL's highly accurate power analysis must be linked to logical and physical implementations to ensure the quality of the final design.

Next-generation design tools

To solve the above problems, the entire design process needs to be further upgraded to become a set of tools that can consider a variety of different effects and design evaluations. Tools must have the ability to transmit intelligent data. For example, the emerging Advanced Library Format (ALF) standard that supports mathematical models can transmit multiple attributes without modifying the original calculation and data format. For new highly complex and demanding designs, it is necessary to plan solutions to problems in the early stages of the design process, because the corrections at this time are the most effective. The links between design, verification, placement and routing, and final physical verification all require consistent exchange of data, without the need to modify data or perform additional calculations.

With ALF, users can generate test vectors to check power consumption and electron migration, and at the same time, they can also test the function of the chip. The test vector can use the probability reference of the extracted chip data to ensure the necessary accuracy. Using this method can carefully examine the entire design process. In the early register-level design process of the design, engineers can minimize signal crosstalk through careful planning, bottom-level planning, and power analysis. The asynchronous clock driver developed for certain parts of the design will reduce the concurrent switching power surge of the entire chip, while at the same time reducing noise and IR drop on the power supply network.

Unfortunately, the existing commercial software tools have very limited application value for next-generation product design.

Although most ASIC manufacturers have their own internal tool development teams, and the main work of these development departments is to integrate some individual tools into a complete process, and design some automated operating environments for these tools so that these tools can be based on Automatic script to run. Since the existing commercial software tools cannot solve the problems faced by the design, in the near future we will see that the number of design tools developed internally by ASIC manufacturers will continue to increase.

However, the problem with the tools developed by ASIC vendors is that these tools require more support and training than commercial software tools, because the tool developers within ASIC vendors are not responsible for making the tools easy to use and maintainable. . They are just trying to provide quick solutions to some of the key problems faced by internal users-that is, the design engineer team.