PCB Technical - Transition tutorial from PROTEL to ALLEGRO

With the increasing complexity of PCB design and the increasing demand for high-speed PCB design, more and more PCB designers and design teams choose Cadence's design platforms and tools. However, because there is no direct conversion tool for Protel data to Cadence data, how to convert the existing design data based on the Protel platform to the Cadence platform has been a problem faced by designers in the platform conversion period for a long time.

On the basis of long-term reality, combined with the characteristics of existing tools, a method for converting Protel schematics and PCBs to the Cadence platform is provided.

1. Tools used

a) Protel DXP SP2

b) Cadence Design Systems, Inc. Capture CIS

c) Cadence Design Systems, Inc. Orcad Layout

d) Cadence Design Systems, Inc. Layout2allegro

e) Cadence Design Systems, Inc. Allegro

f) Cadence Design Systems, Inc. Specctra

2. Protel schematics to Cadence Design Systems, Inc. Capture CIS

We can use the new functions of Protel DXP SP2 to realize the conversion of Protel schematics. Through this function, we can directly convert Protel schematics into Capture CIS.

Here, we only put forward a few precautions that have been summarized through practice.

1) When Protel DXP outputs the Capture DSN file, it does not output package information. In Capture, we will see that the PCB Footprint attributes of all components are empty. This requires us to manually add packaging information to the components, which is also the most time-consuming work in the entire conversion process. When adding package information, pay attention to maintaining package consistency with Protel PCB design, and Cadence's restrictions on package naming. For example, a resistor whose package in Protel is AXIAL0.4 will be modified to AXIAL04 in the conversion of the package library described later. This is because Cadence does not allow "." in the package name; another example is the DB9 connector Packaged in Protel as DB9RA/F, it will be changed to DB9RAF. Therefore, when we add package information to components in Capture, we must take these naming changes into consideration.

2) The hidden pins or pin numbers of some devices will be lost during the conversion process and need to be added in Capture using the library editing method. Generally, the devices that are easy to lose pin numbers are discrete devices such as resistors and capacitors.

3) In the hierarchical design, the bus connected between the modules needs to be named in Capture. Even if such a bus has been named in the parent design in Protel, it must be re-created in Capture to ensure the connection.

4) For devices with multiple parts in a package, pay attention to modifying their tag numbers. For example, a 74ls00, using two of the doors in Protel, the location numbers are U8A, U8B. Such information will be lost in the conversion and needs to be added again.

Basically notice the above points, with the help of Protel DXP, we can convert Protel schematics into Capture. Further promotion, this also provides a way for the existing Protel schematic symbol library to be converted to Capture.

3. Protel package library conversion

Using Protel for PCB design for a long time, we will always accumulate a huge Protel package library that has been tested in practice. When the design platform is changed, how to retain this package library is always a headache. Here, we will use Orcad Layout, and the free Cadence tool Layout2allegro to complete this work.

1) Place the PCB package in an empty PCB in Protel, and output the PCB file in Protel PCB 2.8 ASCII format;

2) Use Orcad Layout to import this Protel PCB 2.8 ASCII file;

3) Use Layout2allegro to convert the generated Layout MAX file into Allegro BRD file;

4) Next, we use Allegro's Export function to output the package library and pad library, and the conversion of the Protel package library to Allegro is completed.

4. Conversion of Protel PCB to Allegro

With the foundation of the previous two steps, we can convert from Protel PCB to Allegro. This conversion process is more precisely a design reproduction process. We will reproduce the layout and routing of Protel PCB in Allegro.

1) Pass the Allegro format netlist generated by Capture in the second step to Allegro BRD as the starting point for our reproduction work;

2) First, we want to reproduce the device layout. Output Place & Pick file in Protel, this file contains complete device position, rotation angle and placement layer information. We can convert it into Allegro's Placement file by simple manual modification. Import this Placement file in Allegro, and we can get the layout.

3) To restore the wiring information, Specctra should be used as a bridge. First, export the Specctra DSN file containing wiring information from Protel. For this DSN file, we should pay attention to the following 2 points:

4) The layer naming in Protel is different from that in Allegro. Please pay attention to using a text editor to make appropriate modifications. For example, the top and bottom layers in Protel are Toplayer and Bottomlayer, while in Allegro these two layers were once called TOP and BOTTOM;

5) Pay attention to check the definition of the via in Specctra and add it to Allegro's rules. Define vias in allegro to output wiring information from Specctra. You can use session, wires, and route files. It is recommended to use the route file, and then import the wiring information to us and the Allegro PCB that reproduces the layout, and we are done from Protel Conversion of PCB to Allegro BRD.

Protel to Allegro conversion method

With the rapid development of today's IT industry, the requirements for hardware equipment are getting higher and higher. Hardware designers are facing the problem of how to design high-speed and high-density PCBs. As the saying goes, if workers want to do their jobs well, they must first sharpen their tools. This is why more and more designers abandon low-end PCB design tools and choose high-performance PCB EDA software provided by companies such as Cadence.

But this kind of change will inevitably bring about problems of one kind or another. Due to early contact and use, there are a large number of Protel users in China. When they choose Cadence high-speed PCB solutions, they all face the problem of how to transplant their Protel designs into Cadence PCB design software.

The problems encountered in this process can be roughly divided into two types: one is that the design is not very complicated, and the designer only wants to use the powerful automatic wiring function of Cadence CCT to complete the wiring work; the other is that the design is complex, and the designer needs to rely on signal-to-noise analysis Tools to simulate the design of signal-to-noise, set up the wiring topology of the network and other tasks.

For the first case, the conversion work to be done is relatively simple, you can use the Protel to CCT conversion tool provided by Protel or Cadence to complete this work. For the second case, the work to be done is relatively complicated, and the method of this transformation will be briefly introduced below.

The analysis object of the Cadence signal-to-noise analysis tool is the brd file of Cadence Allegro, and Allegro can read third-party netlists that meet its requirements. The Telexis format netlists output by Protel meet Allegro's requirements for third-party netlists, so that you can Inject Protel files into Allegro.

Here are two points for the reader's attention. First, Allegro third-party netlists do not allow "." in the $PACKAGE section; second, in Protel, we use the form of BasName[0:N] to represent the bus, and BasName[x] to represent a signal in the bus. The representation of a signal in the bus in the Allegro third-party netlist is Bas NameX. Readers can solve these problems by directly modifying the Telexis netlist output by Protel.

Allegro also needs the device description file Device.txt file of each type of device when injecting the third-party netlist. Its format is as follows:

Package: package type

Class: classtype

Pincount: total pinnumber

Pinused: ...

The commonly used items are PACKAGE, CLASS, and PINCOUNT. PACKAGE describes the package of the device, but Allegro will use the PACKAGE item in the netlist and ignore this item in the device description file when injecting the netlist. CLASS determines the type of the device for signal-to-noise analysis. Cadence divides the device into three categories: IC, IO, and DISCRETE. PINCOUNT indicates the number of pins of the device. For most devices, it is sufficient to include these three items in the Device.txt file.

With third-party netlists and device description files, we can substitute the schematic design in Protel into the Cadence PCB design software in the form of a netlist. Then, designers can use Cadence PCB software to design high-speed and high-density PCBs. The powerful functions of this aspect complete your own design.

If you have done PCB layout work in Protel, Allegro's script function can reproduce the layout in Protcl in Allegro. In Protel, the designer can output a Place & Pick file, which contains the position, rotation angle and information of each device on the top or bottom of the PCB. You can easily generate an Allegro script file from this file., Executing this script in Allegro can reproduce the layout in Protel. The C++ code to complete the conversion of Place & Pick files to Allegro Script files is given below. The author uses this code and only takes a few minutes to transfer a user The PCB layout of more than 800 devices was reproduced in Allegro.

FILE *fp1, *fp2;

::AfxMessageBox("hello");

fp1=fopen("pick.txt", "rt");

if (fp1==NULL) ::AfxMessageBox("Can not open the file!!!");

fp2=fopen("place.txt","wt");

if (fp2==NULL) ::AfxMessageBox("Can not create the file!!!");

char refdes[5], Pattern[5];

float midx,midy,refx,refy,padx,pady,rotation;

char tb[1];

char tmp='"';

fprintf(fp2,"%sn", "# Allegro script");

fprintf(fp2,"%sn", "version 13.6");

fprintf(fp2,"%sn", "place refdes");

while (!feof(fp1)) {

fscanf(fp1,"%s", refdes);

fscanf(fp1,"%s", Pattern);

fscanf(fp1,"%f", &midx);

fscanf(fp1,"%f", &midy);

fscanf(fp1,"%f", &refx);

fscanf(fp1,"%f", &refy);

fscanf(fp1,"%f", &padx);

fscanf(fp1,"%f", &pady);

fscanf(fp1,"%s", tb);

fscanf(fp1,"%f", &rotation);

fprintf(fp2, "fillin %c%s%c n",tmp,refdes,tmp);

if (rotation!=0) {

fprintf(fp2, "rotaten");

fprintf(fp2, "iangle %fn", rotation);

};

char yy=tb[0];

if (yy!='T') fprintf(fp2, "pop mirrorn");

fprintf(fp2, "pick %f %f n", padx,pady);

fprintf(fp2, "next n");

};

fprintf(fp2, "done");

fclose(fp1);

fclose(fp2);

The above briefly introduces the conversion method of Protel to Allegro, and I hope it can be helpful to readers' design work.