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With the continuous development of display technology, true color LCD displays gradually occupy an important position in PCB embedded display systems with their advantages of high resolution, high contrast, and high definition. At present, there are mainly two ways to realize the design and development of LCD controller based on PCB embedded platform: ARM embedded LCD controller and independent control device. However, both of these two implementations have shortcomings. The use of embedded controllers may increase the burden on the PCB processor and limit the display frame rate. The external PCB control devices are not only costly, but also highly specific, which is difficult. Adapt to different types of LCD screens.
Based on this problem, a design scheme of LCD controller based on ARM and FPGA is proposed here. On the one hand, this design scheme can increase the writing rate of video memory and reduce the burden on the processor by operating the Framebuffer device under LINUX OS. On the one hand, FPGA is used to realize the design of LCD controller, with short development cycle, low power consumption, and flexible portability, which can be applied to different small and medium-sized LCD screens.
The system mainly consists of a microcontroller, FPGA (LCD controller), storage unit, and peripheral interface. The block diagram of the system is shown in Figure 1.
The working process of the system: under the action of the timing control signal generated by the timing generating circuit inside the FPGA, the LCD controller reads the data required for display from the microcontroller through the Framebuffer interface and stores it in the display buffer SRAM. At the same time, the LCD display reads the display data from the display memory SRAM, and directly displays the data information in real time through the data format conversion circuit.
The LCD controller is implemented based on FPGA. This program uses Altera's Cvclone (hurricane) series EPlC6Q240. FPGA has a high-speed data transmission I/O interface, which can realize a high-speed display memory reading rate and greatly improve the frame rate of LCD display. At the same time, FPGA is a programmable logic device that can implement complex logic operations and provide complex control timing. The LCD display adopts the LQ035Q3DG01 type TFT-LCD liquid crystal display, the resolution is 320&TImes;240, and the image signal is in RGB format.
Because SRAM has a higher read and write speed, the display cache of this PCB design scheme uses 1 piece of IS61LV51216AL SRAM with a capacity of 512 KB and a read and write speed of about 10ns. And the size of displaying a frame of image is 125 KB (320x240x2/l024), FPGA reads and writes speed to the display memory is about 200 ns, so meet the system requirement.
The main control unit designed and developed by the controller adopts ATMEL's AT9lRM9200 (abbreviated as 9200) as the MCU. The PCB processor is based on the ARM920T core with a working frequency of 180 MHz. The performance can reach 200 MI/s, and the system adopts open source LINUX OS. However, ARM9, as the control terminal of the system, needs to complete a number of tasks such as information collection, processing, and external communication. If the LCD controller also reads data from the memory for display, this will burden the processor and reduce the display cache. The rate of reading data affects the real-time display of the LCD. Therefore, an application method based on the Framebuffer interface under LINUX OS is proposed here, which greatly improves the rate of reading data from the display memory, thereby improving the real-time performance of the entire display system. Figure 3 shows the AT91RM9200 interface circuit connection.
The software design of the system is mainly divided into two parts: LCD controller design based on FPGA and Framebuffer driver design under LINUX OS.
The LCD controller of this design is mainly composed of modules such as cache read and write, MCU interface and LCD timing control.
According to the principle of TFT-LCD display, the main control signals required for display include pixel clock signal, line/field synchronization PCB signal and enable signal. The resolution of the display screen of this scheme is 320x240, and it is required to design the refresh frequency of the LCD display to be 60 Hz, that is, the field synchronization signal (VSYNC) is 60 Hz. Consists of a line synchronization signal, then the period of a line synchronization signal is 1/(60x240) s, and then the line synchronization signal (HSYNC) is 15 kHz. In the same way, the pixel clock signal (CK) is 5MHz.
The FPGA's built-in phase-locked loop IP module (PLL) is used to divide the FPGA 50 MHz clock signal F_CLK by 10 into a 5 MHz pixel clock signal. The state machine method is used to design the timing control module with Verilog hardware description language, which provides the PCB control signals VSYNC, HSYNC and ENAB that meet the timing requirements for the LCD. After the PCB design is completed, the timing simulation is completed in the QuatuslI environment, and the simulation results obtained meet the timing requirements.
SRAM is a video memory module. It can be seen that the PCB data transmission between the LCD controller and the microcontroller is read in under the control of the ARM clock, while the LCD screen reads data from the SRAM under the control of the pixel clock signal CK . Aiming at the problem of PCB data transmission between different clock domains, this solution adopts FPGA design to implement asynchronous FIFO to complete.
