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As the operating frequency of devices becomes higher and higher, the signal integrity problems faced by high-speed PCB designs have become a bottleneck in traditional designs, and engineers are facing increasing challenges in designing complete solutions. Although relevant high-speed simulation tools and interconnection tools can help design designers solve some of the problems, high-speed PCB design also requires continuous accumulation of experience and in-depth exchanges between industries.
The influence of wiring topology on signal integrity
Signal integrity problems may arise when signals are transmitted along transmission lines on high-speed PCB boards. Netizen tongyang of STMicroelectronics asked: For a set of buses (address, data, commands) driving up to 4 or 5 devices (FLASH, SDRAM, etc.), when PCB wiring, the bus arrives at each device in turn, as first Connect to SDRAM, then to FLASH...The bus is still distributed in a star shape, that is, it is separated from a certain place and connected to each device. Which of the two methods is better in terms of signal integrity?
In this regard, some experts pointed out that the influence of wiring topology on signal integrity is mainly reflected in the inconsistent signal arrival time at each node, and the reflected signal also arrives at a certain node at inconsistent time, which causes the signal quality to deteriorate. Generally speaking, the star topology structure can make the signal transmission and reflection delays consistent by controlling several branches of the same length to achieve better signal quality. Before using the topology, the situation of the signal topology node, the actual working principle and the wiring difficulty should be considered. Different buffers have different effects on the reflection of the signal, so the star topology cannot solve the delay of the data address bus connected to FLASH and SDRAM, and thus cannot ensure the quality of the signal; on the other hand, high-speed signals generally For communication between DSP and SDRAM, the rate of FLASH loading is not high, so in high-speed simulation, only the waveform at the node where the actual high-speed signal works effectively is ensured, and there is no need to pay attention to the waveform at FLASH; star topology is compared with daisy chain and other topologies. In other words, wiring is more difficult, especially when a large number of data address signals use star topology.
The impact of pads on high-speed signals
In the PCB, from a design point of view, a via is mainly composed of two parts: the middle hole and the pads around the hole. An engineer named fulonm asked the guest about the impact of pads on high-speed signals. In this regard, the expert said: pads have an impact on high-speed signals, and it affects the impact of similar device packaging on devices. A detailed analysis shows that after the signal comes out of the IC, it passes through the bonding wire, pins, package shell, pad, and solder to the transmission line. All joints in this process will affect the quality of the signal. But in actual analysis, it is difficult to give the specific parameters of the pad, solder and pin. Therefore, the package parameters in the IBIS model are generally used to summarize them. Of course, such analysis can be received at lower frequencies, but for higher frequency signals, higher-precision simulations are not accurate enough. A current trend is to use IBIS's V-I and V-T curves to describe buffer characteristics, and to use SPICE models to describe package parameters.
How to suppress electromagnetic interference
PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to the electromagnetic compatibility (EMC) of electronic products. If emphasizing EMC/EMI in high-speed PCB design, it will help shorten the product development cycle and speed up the time to market. Therefore, many engineers are very concerned about the problem of suppressing electromagnetic interference in this forum. For example, in the EMC test, the harmonics of the clock signal are found to be very serious. Is it necessary to perform special treatment on the power supply pins of the IC that uses the clock signal? At present, only decoupling capacitors are connected to the power supply pins. What aspects should be paid attention to in PCB design to suppress electromagnetic radiation? In this regard, the expert pointed out that the three elements of EMC are radiation source, transmission route and victim. The propagation path is divided into space radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power supply decoupling is to solve the propagation of conduction mode. In addition, necessary matching and shielding are also required.
When answering questions from WHITE netizens, the expert pointed out that filtering is a good way to solve EMC radiation through conduction. In addition, it can also be considered from the aspects of interference sources and victims. In terms of interference source, try to use an oscilloscope to check whether the signal rising edge is too fast, there is reflection or overshoot, undershoot or ringing. If so, you can consider matching; in addition, try to avoid making 50% duty cycle signals, because this kind of signal has no even Sub-harmonics and more high-frequency components. For the victims, measures such as land coverage can be considered.
