PCB Technical - Capacitor placement experience in PCB design

For the placement and installation of capacitors in PCB design, the first thing to mention is the installation distance. The capacitor with the smallest capacitance has the highest resonant frequency and the smallest decoupling radius, so it is placed closest to the chip. The larger capacity can be farther away, and the outermost layer has the largest capacity. However, all capacitors that decouple the chip should be as close as possible to the chip.

Another point to note is that when placing it, it is best to distribute it evenly around the chip, and this must be done for each capacitance level. Usually the arrangement of the power and ground pins is taken into account when the chip is designed, and they are generally evenly distributed on the four sides of the chip. Therefore, voltage disturbances exist all around the chip, and the decoupling must also decouple the entire chip area evenly. If 680pF capacitors are placed on the upper part of the chip, due to the decoupling radius problem, the voltage disturbance at the lower part of the chip cannot be decoupled well.

Capacitor installation

When installing the capacitor, pull out a short lead wire from the pad, and then connect it to the power plane through the via hole, and the same is true for the ground terminal. The current loop flowing through the capacitor is: power plane->via->lead-out line->pad->capacitor->pad->lead-out line->via->ground plane, Figure 2 intuitively shows the current reflux path.

The first method leads out a long lead wire from the pad and then connects to the via hole, which will introduce a large parasitic inductance. This must be avoided. This is the worst installation method.

The second method drills holes at the two ends of the pad next to the pad, which has a much smaller road area than the first method, and the parasitic inductance is also small, which is acceptable.

The third type is to drill holes on the side of the pad, which further reduces the loop area, and the parasitic inductance is smaller than the second type, which is a better method.

The fourth method has holes on both sides of the pad. Compared with the third method, it is equivalent to that each end of the capacitor is connected to the power plane and the ground plane in parallel through vias, which is smaller than the third parasitic inductance. Space permits, try to use this method.

The last method is to directly drill holes on the pads, with the least parasitic inductance, but welding may cause problems. Whether to use it depends on the processing ability and method.

The third and fourth methods are recommended.

Need to emphasize one point: In order to save space, some PCB board design engineers sometimes let multiple capacitors use common vias. Do not do this under any circumstances. It is best to find a way to optimize the design of the capacitor combination and reduce the number of capacitors.

Since the wider the PCB line, the smaller the inductance, the lead-out line from the pad to the via hole should be as wide as possible, and if possible, try to be the same width as the pad. In this way, even if it is a capacitor in a 0402 package, you can also use a 20mil-wide lead wire. The lead wires and vias are installed as shown in Figure 4. Pay attention to the various sizes in the figure.