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1. How to choose EDA tools?
In the current PCB design software, thermal analysis is not a strong point, so it is not recommended to use it. For other functions 1.3.4, you can choose PADS or Cadence. The cost performance is good. Beginners in PLD design can use the integrated environment provided by PLD chip manufacturers, and can use single-point tools when designing more than one million gates.
2. Please recommend an EDA software suitable for high-speed signal processing and transmission.
For conventional circuit design, INNOVEDA's PADS is very good, and there is a matching simulation software, and this type of design often occupies 70% of the applications. When doing high-speed circuit design, analog and digital hybrid circuits, the solution using Cadence should be a software with better performance and price. Of course, Mentor's performance is still very good, especially its design flow management should be the best. (Wang Sheng, Technical Expert of Datang Telecom)
3. Explanation of the meaning of each layer of the PCB board
Topoverlay ---- The name of the top device, also called top silkscreen or top component legend, such as R1 C5,
IC10.bottomoverlay----similarly to multilayer-----if you design a 4-layer board, you place a free pad or via, define it as a multilayer, then its pad will automatically appear on the 4 layers, if You only define it as the top layer, then its pad will only appear on the top layer.
4. What aspects should be paid attention to in high frequency PCB design, routing and layout above 2G?
High-frequency PCBs above 2G belong to the design of radio frequency circuits and are not within the scope of discussion of high-speed digital circuit design. The layout and routing of the radio frequency circuit should be considered together with the schematic, because the layout and routing will cause distribution effects. Moreover, some passive components in the design of radio frequency circuits are realized through parameterized definitions and special-shaped copper foils. Therefore, EDA tools are required to provide parametric devices and edit special-shaped copper foils. Mentor's boardstation has a special RF design module that can meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The most famous in the industry is Agilent's eesoft, which has a good interface with Mentor's tools.
5. For high frequency PCB design above 2G, what rules should be followed for microstrip design?
The design of RF microstrip line requires 3D field analysis tools to extract the transmission line parameters. All rules should be specified in this field extraction tool.
6. For the PCB with all digital signals, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), in order to ensure sufficient drive capacity, what kind of circuit should be used for protection?
To ensure the driving capability of the clock, it should not be realized through protection, and the clock driving chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Adopt the clock to drive the chip, change one clock signal into several, adopt the point-to-point connection. When selecting the drive chip, in addition to ensuring that it is basically matched with the load, the signal edge meets the requirements (usually the clock is an edge valid signal). When calculating the system timing, the delay of the clock in the drive chip should be counted.
7. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?
The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board will increase the signal wiring length. And the grounding power supply of the single board is also a problem. If long-distance transmission is required, differential signals are recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and it is unnecessary.
8. 27M, SDRAM clock lines (80M-90M). The second and third harmonics of these clock lines are just in the VHF band, and the interference will be great after the high frequency enters from the receiving end. In addition to shortening the line length, what other good methods are there?
If the third harmonic is large and the second harmonic is small, it may be because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle. In addition, if it is a unidirectional clock signal, the source terminal series matching is generally used. This can suppress secondary reflections, but will not affect the clock edge rate. The source matching value can be obtained using the formula below.
9. In the PCB layout and design, what is the topological structure of the trace?
Topology, and some are also called routing order. For the routing order of a multi-port connection network.
10. How to adjust the routing topology to improve signal integrity?
This kind of network signal direction is more complicated, because for unidirectional, two-way signals, and different level types of signals, the topology influences are different, and it is difficult to say which topology is beneficial to the signal quality. And when doing pre-simulation, which topology to use is very demanding on engineers, requiring understanding of circuit principles, signal types, and even wiring difficulty.
