PCB Technical - Power supply for isolated switch PCB board layout design

A good PCB board design optimizes efficiency, mitigates thermal stress, and minimizes noise and effects between traces and components. It all stems from the designer's understanding of the current conduction paths and signal flow in the power supply. When a prototype power strip was first powered up, it was not only functional, but also quiet and low heat. However, this is rare. A common problem with switching power supplies is "unstable" switching waveforms. Sometimes, the waveform jitter is in the acoustic range, and the magnetic components produce audible noise. If the problem is with the layout of the printed circuit board, it can be difficult to figure out the cause. Therefore, correct PCB layout in the early stage of switching power supply design is very critical. Power supply designers need to have a good understanding of the technical details, as well as the functional requirements of the final product. Therefore, from the very beginning of a board design project, the power supply designer should work closely with the PCB layout designer on critical power supply layouts. A good layout design optimizes power efficiency and mitigates thermal stress; more importantly, it minimizes noise and trace-component interactions. To achieve these goals, designers must understand the current conduction paths and signal flow within the switching power supply. To achieve a proper layout design for a non-isolated switching power supply, it is important to keep these design elements in mind.

Floorplan
For an embedded dc/dc power supply on large printed circuit boards, obtaining voltage regulation, load transient response, and system efficiency requires placing the power supply output close to the load device, minimizing interconnect impedance and conduction voltage drop on the PCB traces . Ensure good airflow to limit thermal stress; if forced air cooling is available, place the power supply close to the fan. Additionally, large passive components such as inductors and electrolytic capacitors must not block airflow through low profile surface mount semiconductor components such as power MOSFETs or PWM controllers. To prevent switching noise from interfering with the analog signals in the system, avoid placing sensitive signal lines under the power supply as much as possible; otherwise, an internal ground plane needs to be placed between the power supply layer and the small signal layer for shielding. The key is to plan for the location of the power supplies, as well as the board space requirements, in the early design and planning stages of the system. Sometimes designers ignore this advice and focus on the more "important" or "exciting" circuits on large system boards. Power management is seen as an afterthought, and placing power supplies in excess space on the board is detrimental to efficient and reliable power supply designs. For multi-layer boards, a good approach is to place a DC ground or DC input/output voltage layer between the high-current power component layers and the sensitive small-signal trace layers. The ground plane or DC voltage plane provides an AC ground that shields small signal traces from noisy power traces and power components. As a general rule, neither the ground plane nor the DC voltage plane of a multilayer PCB should be separated. If this separation is unavoidable, the number and length of traces on these layers should be minimized, and the traces should be placed in the same direction as the high current to minimize the impact.

Power stage layout
The switching power supply circuit can be divided into two parts: power stage circuit and small signal control circuit. Power stage circuits contain components that carry high currents, and typically these components are placed first, followed by the placement of small-signal control circuits at specific points in the layout. High-current traces should be short and wide to minimize PCB inductance, resistance, and voltage drop. This aspect is especially important for those traces with high di/dt pulse currents. The high frequency decoupling capacitor CHF should be a ceramic capacitor of 0.1uf~10uf, X5R or X7R dielectric, which has extremely low ESL (effective series inductance) and ESR (equivalent series resistance). Larger capacitive dielectrics (like Y5V) may have large drops in capacitance value at different voltages and temperatures, and are therefore not CHF materials. This problem can be solved by adding two 1-mist high-frequency ceramic capacitors at the input end of each channel. The capacitors isolate the thermal loop area of each channel and make it easier to use. The switching waveform is stable even at load currents up to 30A.

High DV/DT switch area
This junction is rich in high frequency noise components and is a powerful source of EMI noise. To minimize coupling capacitance between the switch junction and other noise-sensitive traces, you may want to keep the SW copper area as small as possible. However, in order to conduct a large inductor current and provide a heat dissipation area for the power MOSFET, the PCB area of the SW node should not be too small. It is generally recommended to place a grounded copper foil area under the switch junction to provide additional shielding. If there is no heat sink for surface mount power MOSFETs and inductors in the design, the copper foil area must have sufficient heat dissipation area. For DC voltage junctions (such as input/output voltage and power ground), it is reasonable to make the copper foil area as large as possible. Multiple vias help further reduce thermal stress. Determining the appropriate copper area for a high dv/dt switch junction requires a design balance between minimizing dv/dt-related noise and providing good MOSFET heat dissipation.

Power pad form
For decoupling capacitors, the positive and negative vias should be as close to each other as possible to reduce the ESL of the PCB. This is especially effective for low ESL capacitors. Small value, low ESR capacitors are generally more expensive, and incorrect pad patterns and poor traces can degrade their performance and increase overall cost. In general, a reasonable pad form can reduce PCB noise, reduce thermal resistance, and minimize trace impedance and voltage drop of high-current components. A common misunderstanding when laying out high current power components is the incorrect use of thermal relief. Unnecessary use of hot air pads will increase the interconnect impedance between power components, resulting in greater power loss and reducing the decoupling effect of small ESR capacitors. If vias are used to conduct large currents during layout, make sure they have a sufficient number to reduce impedance. Also, do not use hot air pads for these vias.

Control circuit layout
Keep control circuits away from noisy switch copper areas. For a buck converter, it is a good idea to place the control circuit close to VOUT+, while for a boost converter, the control circuit should be placed close to VIN+, allowing the power traces to carry continuous current. If space permits, keep a small distance (0.5 inch to 1 inch) between the control IC and the power MOSFETs and inductors (both high noise and high thermal components). If space is tight and you are forced to place the controller close to the power MOSFETs and inductor, special care must be taken to isolate the control circuit from the power components with a ground plane or ground traces. The control circuit should have a separate signal (analog) ground from the power stage ground. If there are separate SGND (signal ground) and PGND (power ground) pins on the controller IC, they should be routed separately. For the control IC with integrated MOSFET driver, SGND should be used for the IC pins of the small signal part. Only one connection point is required between signal ground and power ground. A reasonable approach is to return the signal ground to a clean spot on the power plane. Two grounds can be achieved by just connecting two ground traces under the controller IC. Figure 12 (omitted) shows the recommended LTC3855 power-to-ground isolation method. In this example, the IC has an exposed ground pad. This pad should be soldered to the PCB to minimize electrical and thermal resistance. Multiple vias should be placed in the ground pad area. The decoupling capacitors of the control IC should be placed close to their respective pins. To minimize connection impedance, it is a good idea to place decoupling capacitors directly on the pins, not through vias. As shown in Figure 12 (omitted), the LTC3855 pins that should be placed close to the decoupling capacitor are the current detection pin Sense+/Sense-, the compensation pin ITH, the signal ground SGND, the feedback voltage divider pin FB, and the IC VCC voltage pin Pin INTVCC, and power ground pin PGND.

Loop Area and Crosstalk
Two or more adjacent conductors can create capacitive coupling. A high dv/dt on one conductor couples out a current on the other conductor through parasitic capacitance. To reduce coupling noise from the power stage to the control circuit, keep noisy switch traces away from sensitive small signal traces. If possible, route high-noise traces on separate layers from sensitive traces, and use the internal ground plane as a noise shield. If space permits, the control IC should be kept a small distance (0.5 inches to 1 inch) from the power MOSFET and the inductor, which are both noisy and heat-generating. When routing gate drive signals, using short, wide traces helps minimize impedance in the gate drive path. Place the high FET driver traces TG and SW with the proper loop area to minimize inductance and high dv/dt noise. Likewise, the low FET driver trace BG should be placed close to a PGND trace. If a PGND plane is placed under the BG trace, the AC ground return current of the low FET will automatically couple into a path close to the BG trace. AC current will flow to the loop/impedance it finds. At this point, the low gate driver does not require a separate PGND return trace. The solution is to minimize the number of layers that the gate drive traces pass through, which prevents gate noise from propagating to other layers. Of all small signal traces, the current sense traces are sensitive to noise. The amplitude of the current detection signal is usually less than 100mV, which is comparable to the amplitude of the noise. Taking the LTC3855 as an example, the Sense+/Sense- traces should be placed in parallel with spacing (Kelvin detection) to minimize the chance of picking up di/dt related noise. Also, filter resistors and capacitors for current sense traces should be as close as possible to the IC pins. The filtering effect of this structure when there is noise injected into long sense lines.

Choice of trace width
Current levels and noise susceptibility are the same for specific controller pins, so specific trace widths must be selected for different signals. Usually, the small signal network can be narrower, using 10mil~15mil width traces. High-current networks (gate drive, VCC, and PGND) should use short, wide traces. The traces for these nets are recommended to be at least 20mil wide on PCB board.