PCB Technical - Understand PCB signal integrity solutions

Signal integrity problems are not caused by a single factor, but are caused by multiple factors in PCB design. The main signal integrity problems include reflection, ringing, ground bounce, crosstalk, etc. The following mainly introduces crosstalk and reflection Solution.

3.1 Crosstalk score

Crosstalk refers to the undesirable voltage noise interference caused by electromagnetic coupling to adjacent transmission lines when the signal propagates on the transmission line. Excessive crosstalk may cause false triggering of the circuit and cause the system to fail to work normally.

Since the crosstalk is inversely proportional to the line spacing, it is directly proportional to the parallel length of the line. The crosstalk changes with the load of the circuit. For the same topology and wiring, the greater the load, the greater the crosstalk. Crosstalk is proportional to the signal frequency. In digital circuits, the edge changes of the signal have the greatest impact on crosstalk. The faster the edge changes, the greater the crosstalk.

In view of the above characteristics of crosstalk, it can be summarized into the following methods to reduce crosstalk:

(1) Reduce the transition rate of the signal edge when possible. When selecting devices, while meeting the design specifications, slow devices should be selected as much as possible, and the mixed use of different types of signals should be avoided, because fast-changing signals have potential crosstalk hazards for slow-changing signals.

(2) The crosstalk caused by capacitive coupling and inductive coupling increases with the increase of the load impedance of the interfered line, so reducing the load can reduce the influence of coupling interference.

(3) When the wiring conditions permit, try to reduce the parallel length between adjacent transmission lines or increase the distance between capacitive coupling wires, such as adopting the 3W principle (the distance between the wires must be a single wire 3 times the width or the distance between two traces must be greater than 2 times the width of a single trace). A more effective method is to isolate the wires with ground wires.

(4) Inserting a ground wire between adjacent PCB signal lines can also effectively reduce capacitive crosstalk. This ground wire needs to be connected to the ground every 1/4 wavelength.

(5) Inductive coupling is difficult to suppress, so try to reduce the number of loops, reduce loop area, and avoid sharing the same wire for signal loops.

(6) The signal layer traces of two adjacent layers should be vertical, avoid parallel traces as much as possible to reduce crosstalk between layers.

(7) The surface layer has only one reference layer, and the coupling of the surface layer wiring is stronger than that of the middle layer. Therefore, signals that are more sensitive to crosstalk should be placed on the inner layer as much as possible.

(8) Through termination, the far end and near end of the transmission line, and the terminal impedance are matched with the transmission line, which can greatly reduce crosstalk and reflection interference.

3.2 Reflection analysis

When a signal propagates on a transmission line, as long as it encounters an impedance change, reflection will occur. The main method to solve the reflection problem is to perform terminal impedance matching.

3.2.1 Typical transmission line termination strategy

In the high-speed digital system, the impedance mismatch on the transmission line will cause signal reflection. The method to reduce and eliminate the reflection is to perform terminal impedance matching at the transmitting end or the receiving end according to the characteristic impedance of the transmission line, so that the source reflection coefficient or the load reflection coefficient is O. If the length of the transmission line meets the following conditions, termination technology should be used:

L>tr/2tpd. In the formula, L is the length of the transmission line; tr is the rise time of the source signal; tpd is the load transmission delay per unit length on the transmission line.

The termination of PCB transmission lines usually adopts two strategies: match the load impedance with the impedance of the transmission line, that is, parallel termination; match the source impedance with the impedance of the transmission line, that is, serial termination.

(1) Parallel termination

Parallel termination is mainly to connect the pull-up or pull-down impedance as close as possible to the load end to achieve impedance matching of the terminal. According to different application environments, parallel termination can be divided into several types as shown in Figure 2.

(2) Serial termination

Serial termination is realized by inserting a resistor into the transmission line as close to the source as possible. Serial termination is to match the impedance of the signal source. The resistance of the inserted serial resistor plus the output impedance of the driving source should be Greater than or equal to the transmission line impedance.

This strategy suppresses the signal reflected from the load (input high impedance at the load end, not absorbing energy) by making the source end reflection coefficient zero, and then reflecting back from the source end to the load end.

3.2.2 Termination technology of different process devices

Impedance matching and termination technical solutions vary with the interconnection length and the series of logic devices in the circuit. Only for the specific situation, the correct and appropriate termination method can be used to effectively reduce the signal reflection.

Generally speaking, for a CMOS process drive source, its output impedance value is relatively stable and close to the impedance value of the transmission line, so using serial termination technology for CMOS devices will achieve better results; while the TTL process drive source is The output impedance is different when the output logic is high and low.

At this time, using the parallel Thevenin termination scheme is a better strategy; ECL devices generally have very low output impedance. Therefore, it is the ECL circuit to use a pull-down termination resistor at the receiving end of the ECL circuit to absorb energy. Universal termination technology.

Of course, the above method is not absolute. The difference in the specific circuit, the selection of the network topology, and the number of loads at the receiving end are all factors that can affect the termination strategy. Therefore, when implementing a circuit termination plan in a high-speed circuit, you need to Choose the appropriate termination scheme according to the situation to obtain the best termination effect.

4. Signal integrity analysis and modeling

Reasonable circuit modeling and simulation is the most common signal integrity solution. In high-speed circuit design, simulation analysis shows more and more advantages. It gives designers accurate and intuitive design results, which is convenient for early detection of problems and timely modification, thereby shortening design time and reducing design costs. There are three commonly used models: SPICE model, IBIS model, and Verilog-A model.

SPICE is a powerful general-purpose analog circuit simulator. It consists of two parts: Model Equation and Model Parameters.

Since the model equation is provided, the SPICE model can be very closely connected with the algorithm of the simulator, and better analysis efficiency and analysis results can be obtained; the IBIS model is specifically used for PCB board-level and system-level digital signal integrity Analyzed model.

It uses the form of I/V and V/T tables to describe the characteristics of digital integrated circuit I/O units and pins. The analysis accuracy of the IBIS model mainly depends on the number of data points and the accuracy of the data in the 1/V and V/T tables. Compared with the SPICE model, the IBIS model has a small amount of calculation.

5. Simulation verification

The example circuit of the asynchronous transceiver is used to show the results. In the simulation environment, the excitation signal is set to 50 ns, the power supply is set to 5V, and the other settings are default. The simulation of the U3-5 pin of the RTSB network is performed. The simulation situation is shown in Figure 3:

Curve a is the signal waveform before termination, and it can be seen that there is serious signal reflection; curves b and c are the signal waveforms after ground termination resistance, and the termination resistance values are different; curve d is the signal waveform after Thevenin termination It can be seen from the figure that the termination resistor can basically eliminate the reflection. The disadvantage is that the termination resistor to the ground causes the ground high level voltage to drop, and the termination resistor to the power supply causes the power low level to rise.

Based on the continuous development of microelectronics technology, the use of high-speed devices and the design of high-speed digital systems are increasing. The system data rate, clock rate and PCB density are constantly increasing, and the design requirements for PCB boards are also getting higher and higher. It is a signal integrity problem.

To ensure that the PCB has good signal integrity, it is necessary to synthesize a variety of influencing factors, rationally layout and route, thereby improving product performance.