The thermal management challenge will become even more daunting when it comes to installing PCB board containing multi-core processors. Although each processor core in the processor array may consume less power and thus dissipate less heat than a single-core processor, the net effect on large computer servers is to add more to the computer system in the data center Heat dissipation. In short, run more processor cores on a given area of the PCB.
Another thorny IC thermal management issue involves hot spots that appear on chip packaging. The heat flux can be as high as 1000Wcm2, which is a difficult-to-track state.
PCB plays an important role in thermal management, so thermal design layout is required. Design engineers should keep high-power components as far apart as possible from each other. In addition, these high-power components should be as far away from the corners of the PCB as possible, which will help maximize the PCB area around the power components and accelerate heat dissipation.
Soldering the exposed power pad to the PCB is a common practice. Generally speaking, the exposed pad type power pad can conduct about 80% of the heat generated through the bottom of the IC package and into the PCB. The remaining heat will be dissipated from the sides and leads of the package.
Thermal assistant PCB design engineers can now turn to many improved thermal management products for help. These products include radiators, heat pipes and fans, which can be used to achieve active and passive convection, radiation and conduction cooling. Even the interconnection method of mounting chips on the PCB helps to alleviate the heat dissipation problem.
For example, the common exposed pad method used to interconnect IC chips to PCBs may increase heat dissipation issues. When the exposed path is soldered to the PCB, the heat will quickly escape the package and enter the PCB board, and then dissipate into the surrounding air through the various layers of the PCB board.
Texas Instruments TI has invented a PowerPAD method that can mount IC die on a metal disk. This die pad will support the die during the manufacturing process and act as a good heat dissipation path to dissipate heat from the chip.
Matt Romig, TI's analog packaging product manager, pointed out that TI’s PowerStack method is the first 3D packaging technology that can stack high-side vertical MOSFETs. This technology integrates high-side and low-side MOSFETs fixed in position by copper clips, and uses ground potential exposed pads to provide thermally optimized designs. The use of two copper clips to connect the input and output voltage pins can form a more integrated flat square leadless QFN package. The thermal management of power devices is more challenging. The need for higher frequency signal processing and reduced package size has gradually marginalized traditional cooling technology. KaverAzar, President and CEO of AdvancedThermalSolutions, suggested using embedded thin-film thermoelectric devices with water-cooled microchannels.
Azar conceived such a solution: to minimize the maximum thermal resistance in the heat dissipation path, diffusion thermal resistance, by binding a heat sink directly to the microprocessor die.
This method can dissipate the heat accumulated on the small microprocessor die to a larger heat sink base, and then dissipate the heat to the surrounding environment. This built-in forced heat spreader integrates micro-channels and mini-channels in a silicon package. The water flow rate in the channel is about 05 to 1 liter min.
The simulation results show that, on the 1010mm die in the ball grid array BGA package, a 120120mm heat sink chassis area can produce a thermal resistance of 0055KW. The use of heat dissipation materials with thermal conductivity equal to or greater than diamond can produce a thermal resistance of 0030KW.
Paul Magill, the vice president of marketing and business development at Nextreme Thermal Solutions, also recommended thermoelectric cooling technology and declared that cooling should start at the chip level. The company provides localized thermal management technology deep inside electronic components. This technology uses a micro-film thermoelectric eTEC structure called a heat pump. This active heat dissipation material is embedded in flip chip interconnects such as copper pillar solder bumps for use in electronic packaging.
Achieving localized cooling at the chip wafer, die, and package level can produce important economic benefits. For example, in a data center with thousands or hundreds of advanced microprocessors, this method is more efficient than using a more expensive and larger air-conditioning system to dissipate heat.
In some devices such as LEDs, the combined use of passive and active cooling technologies can improve device performance and lifetime. For example, the use of a fan in a radiator can generally reduce the thermal resistance to 05W, which is a significant improvement compared to the typical 10W achieved by using a passive cooling radiator alone.
Repeated simulation of thermal control has been and will continue to be one of the limiting factors in achieving higher IC performance. In these smaller and smaller ICs and their packages, space is becoming more and more valuable, and there is almost no space left to help with cooling. This forces design engineers to consider the use of external cooling technology and continuously improved new cooling materials.
In any case, the basic premise is still true:PCB design engineers must pay more attention to thermal science to achieve optimal cooling solutions. The whole process should start with thermal analysis software, which is much earlier than when the design is put into production.