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1. Whether the information received in the process is complete (including: schematic diagram, *.brd file, bill of materials, PCB design instructions, PCB design or change requirements, standardization requirements, process design instructions)
2. Confirm that the PCB template is up to date
3. Confirm that the positioning device position of the template is correct
4. Whether the PCB design description, PCB design or change requirements, and standardization requirements are clear
5. Confirm that the forbidden placement of components and wiring areas on the outline drawing have been reflected on the PCB template
6. Compare the outline drawings, confirm that the dimensions and tolerances marked on the PCB are correct, and that the definitions of metallized holes and non-metallized holes are accurate
7. After confirming that the PCB template is accurate, it is best to lock the structure file to avoid misoperation and move the position
Post-layout inspection phase
a. Device inspection
8. Confirm whether all device packages are consistent with the company's unified library, and whether the package library has been updated (use viewlog to check the running results). If they are inconsistent, be sure to Update Symbols
9. Mother board and daughter board, single board and back board, confirm that the signal is corresponding, the position is corresponding, the connector direction and the silk screen identification are correct, and the daughter board has measures to prevent mis-insertion, and the components on the daughter board and the mother board should not interfere
10. Are the components 100% placed?
11. Open the place-bound of the TOP and BOTTOM layers of the device, and check whether the DRC caused by the overlap is allowed
12. Is the Mark point sufficient and necessary?
13. Heavier components should be placed close to the support point or edge of the PCB to reduce the warpage of the PCB
14. It is better to lock the devices related to the structure after they are deployed to prevent misoperation and movement
15. Within 5mm of the crimp socket, no components whose height exceeds the height of the crimp socket on the front side, and no components or solder joints on the back side
b. Function check
16. Whether the digital circuit and analog circuit components of the digital-analog hybrid board have been separated during the layout, and whether the signal flow is reasonable
17. A/D converters are placed across analog-to-digital partitions.
18. Is the clock device layout reasonable?
19. Is the layout of high-speed signal devices reasonable?
20. Whether the termination device has been placed reasonably (source matching series resistance should be placed at the driving end of the signal; middle matching series resistance should be placed in the middle position; terminal matching series resistance should be placed at the receiving end of the signal)
21. Are the number and location of decoupling capacitors of IC devices reasonable?
22. The signal lines use planes with different levels as reference planes. When crossing the plane division area, whether the connection capacitance between the reference planes is close to the signal routing area.
c. fever
23. Keep heat-sensitive components (including liquid medium capacitors, crystal oscillators) away from high-power components, radiators and other heat sources as much as possible
24. Whether the layout meets the thermal design requirements and heat dissipation channels (implemented according to the process design documents)
d. power supply
25. Is the IC power supply too far away from the IC?
26. Is the layout of the LDO and surrounding circuits reasonable?
27. Is the layout of the surrounding circuit such as the module power supply reasonable?
28. Is the overall layout of the power supply reasonable?
e. Rule setting
29. Are all simulation constraints added to the Constraint Manager correctly?
30. Whether the physical and electrical rules are set correctly (pay attention to the restriction settings of the power supply network and the ground network)
31. Is the spacing setting of Test Via and Test Pin sufficient?
Post-wiring inspection phase
f. Digital Model
31. Whether the wiring of the digital circuit and the analog circuit are separated and whether the signal flow is reasonable
32. If the ground is divided for A/D, D/A and similar circuits, do the signal lines between the circuits go from the bridge point between the two grounds (except for differential lines)?
33. The signal line that must cross the gap between the divided power supplies should refer to a complete ground plane.
g. Clock and high-speed part
34. Is the impedance of the high-speed signal line consistent in all layers?
35. Do high-speed differential signal lines and similar signal lines have the same length, symmetrical, and parallel lines nearby?
36. Make sure that the clock line goes to the inner layer as much as possible
37. Confirm whether the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to the 3W principle as far as possible
H (H is the height of the signal line from the reference plane)
38. Do clock lines and high-speed signal lines avoid passing through dense via areas or routing between device pins?
39. Whether the differential pair, high-speed signal line, and various types of BUS have met (SI constraint) requirements
Processing file
i. Drilling pattern
40. Whether the PCB thickness, number of layers, silk screen color, warpage, and other technical specifications of Notes are correct
41. Whether the layer name, stacking sequence, dielectric thickness, and copper foil thickness of the laminate diagram are correct; whether impedance control is required and whether the description is accurate. Whether the layer name of the overlay image is consistent with the gerber file name
42. Turn off the Repeat code in the setting table, and the drilling accuracy should be set to 2-5
43. Whether the hole table and drilling file are up-to-date (when the hole is changed, it must be regenerated)
44. Whether there is an abnormal hole diameter in the hole table, whether the hole diameter of the crimping part is correct; whether the hole diameter tolerance is marked correctly
45. Are the vias of fortress holes listed separately and marked "filled vias"
j. Light painting
46. The output of gerbera files should be in RS274X format as far as possible, and the precision should be set to 5:5
47, art_aper. Is txt up to date (274X may not be needed)
48. Whether there is an abnormal report in the log file of the output gerber file
49. Confirmation of the edges and islands of the negative film layer
50. Use the gerber inspection tool to check whether the gerber file is consistent with the PCB (the revision must be compared with the comparison tool)
Full set of documents
51. PCB file: product model_specification_single board code_version number. brd
52. Backplane liner design file: product model_specification_single board code_version number-CB [-T/B]. brd
53, PCB processing file: PCB code. zip (including the gerber file, aperture table, drilling file and ncdrill.log of each layer; the jigsaw puzzle file *.dxf provided by the craft), and the backing board file: PCB code-CB [-T/B]. zip (including drill.art, *.drl, ncdrill.log)
54. Process design documents: product model_specification_single board code_version number-GY. doc
55, SMT coordinate file: product model_specification_single board code_version number-SMT. txt, (when outputting coordinate files, make sure to select Body center. Only when it is confirmed that the origin of all SMD device libraries is the device center, can you select Symbol origin)
56, PCB board structure file: product model_specification_single board code_version number-MCAD. zip (contains the .DXF and .EMN files provided by the structural engineer)
57. Test file: product model_specification_single board code_version number-TEST. ZIP (contains the coordinate file of testprep.log and untest.lst or *.drl test points)
standardization
58. Confirm that the cover and home page information is correct 59. Confirm that the drawing sequence number (corresponding to the sequence assignment of each layer of the PCB) is correct
60. Confirm that the PCB code on the drawing frame is correct
