PCB Technical - Analysis of Crosstalk Suppression in Small Pitch QFN Package PCB Design

I. Introduction

With the development trend of high-speed and high-density circuit design, QFN packages have been applied with 0.5mm pitch or even smaller pitch. The problem of crosstalk in the fan-out area of PCB traces introduced by small-pitch QFN packaged devices has become more and more prominent as the transmission rate increases. For high-speed applications of 8Gbps and above, attention should be paid to avoiding such problems and providing more margin for high-speed digital transmission links. This article analyzes the method of suppressing crosstalk introduced by the small-pitch QFN package in PCB design, and provides a reference for this type of design.

2. Problem analysis

In PCB design, QFN packaged devices usually fan out from the TOP or BOTTOM layer using microstrip lines. For the small-pitch QFN package, it is necessary to pay attention to the distance between the microstrip lines and the length of the parallel travel line in the fan-out area.

The line width/line spacing of the differential line is: 8/10, the line distance is 7 mils from the reference layer, and the board is FR4.

It can be seen from the simulation results that even in the case of short parallel lines, the near-end crosstalk of the differential port D1 to D2 exceeds -40dB at 5GHz, -32dB at 10GHz, and the far-end crosstalk reaches -40dB at 15GHz. . For 10Gbps and above applications, the crosstalk here needs to be optimized to control the crosstalk below -40dB.

Three, optimization plan analysis

For PCB design, a more direct optimization method is to use tightly coupled differential traces, increase the trace spacing between differential pairs, and reduce the parallel travel distance between differential pairs.

From the optimized simulation results, it can be seen that using tight coupling and increasing the spacing between differential pairs can reduce the near-end crosstalk between differential pairs by 4.8~6.95dB in the frequency range of 0~20G. The far-end crosstalk is reduced by about 1.7~5.9dB in the frequency range of 5G~20G.

In addition to increasing the spacing between the differential pairs and reducing the parallel distance when routing, we can also adjust the distance between the differential line routing layer and the reference plane to suppress crosstalk. The closer it is to the reference layer, the better it is to suppress crosstalk. Based on the tightly coupled routing method, we adjusted the distance between the TOP layer and its reference layer from 7 mils to 4 mils.

It is worth noting that when we adjust the distance between the trace and the reference plane, the impedance of the differential line also changes, and the differential trace needs to be adjusted to meet the target impedance requirements. When the distance between the SMT pad of the chip and the reference plane becomes smaller, the impedance will also become lower. It is necessary to hollow out the reference plane of the SMT pad to optimize the impedance of the SMT pad. The specific size of the hollow out needs to be determined by simulation based on the stacking situation.

It can be seen from the simulation results that after adjusting the distance between the trace and the reference plane, using tight coupling and increasing the spacing between the differential pairs can reduce the near-end crosstalk between the differential pairs by 8.8~12.3 in the frequency range of 0~20G. dB. The far-end crosstalk is reduced by 2.8~9.3dB in the range of 0~20G.

Fourth, the conclusion

Through simulation optimization, we can reduce the near-end differential crosstalk caused by the small-pitch QFN package on the PCB by 8~12dB, and the far-end crosstalk by 3~9dB, providing more margin for the high-speed data transmission channel. The crosstalk suppression method involved in this article can be comprehensively considered when formulating PCB wiring rules and stacking, and avoid the risk of crosstalk caused by the small-pitch QFN package at the early stage of PCB design.