PCB Technical - PCB process high-speed PCB wiring attention

PCB process high-speed PCB wiring attention

Question: What is the definition of high-speed system?
Answer: The high-speed digital signal is determined by the edge speed of the signal. Generally, it is considered as a high-speed signal when the rise time is less than 4 times the signal transmission delay. The usual high-frequency signal refers to the signal frequency. The design and development of high-speed circuits should have knowledge of signal analysis, transmission lines, and analog circuits. Wrong concept: 8kHz frame signal is a low-speed signal.
Question: In high-speed PCB design, the automatic routing function is often used. How can I achieve automatic routing effectively?

Answer: In a high-speed circuit board, you can't just look at the speed and distribution rate of the router. At this time, it also depends on whether it can accept high-speed rules, such as requiring equal length from T-shaped contacts to each terminal. At this time, Cadence's SPECCTRA It can solve the problem of high-speed wiring very well. Many routers cannot accept or can only accept very few high-speed rules.
Question: In high-speed PCB design, what is the relationship between crosstalk and the speed of the signal line, the direction of the trace, etc.? What design indicators need to be paid attention to to avoid crosstalk and other problems?
Answer: Crosstalk will affect the edge rate. Generally speaking, when a group of buses have the same transmission direction, the crosstalk factor will slow down the edge rate. When the transmission direction of a group of buses is not the same, the crosstalk factor will make the edge rate faster. Controlling crosstalk can be achieved by controlling the line length, line spacing, line stacking, and source matching. Question: For high-speed systems, what should be paid attention to when wiring multi-layer circuit boards? What are the principles for the definition of the functions of each layer? Answer: Pay attention to the arrangement of power and ground planes, and ensure that the wiring layer has the same impedance. The key signals should be routed as far as possible with a plane layer on both sides. Do not split across planes. It is generally determined according to the actual situation. The power supply and the ground are connected with the power supply and the ground plane through holes nearby.

Question: On multilayer circuit boards, what measures can reduce the mutual interference between layers and improve the signal quality?
Answer: Mainly to solve the problems of impedance control, matching, trace return, power integrity, EMC, etc. Reducing the inter-layer interference can reduce the distance between the wiring layer and the plane layer, increase the distance between the wiring layers, and try to avoid parallel wiring in the adjacent wiring layers. There are many ways to list them.
Question: Regarding digital power, analog power, digital ground and analog ground, how do you divide them in PCB design?
Answer: The power supply is connected through a filter circuit, and the digital and analog are separated. The digital and analog grounds depend on the specific chip, some require separate, single-point connection, and some do not need to be separated.
Question: The backplane only provides one ground, which is a digital ground, and there are both analog and digital parts on the plug-in card. How to connect this analog ground?
Answer: Depending on the chip requirements of the analog part of your plug-in card, you can generally separate the digital and analog grounds on the plug-in card, connect the plug-in card at a single point, and connect the digital ground of the plug-in card to the digital ground of the backplane.

Question: How to consider impedance matching in high-speed PCB design? In multi-layer circuit board design, how to calculate the characteristic impedance of the internal signal layer? How to match the input impedance of 50Ω and the output impedance of 75Ω?
Answer: Impedance matching needs to be calculated based on line width, line thickness, sheet structure, etc. Sometimes series or parallel resistance must be added to achieve matching. The internal signal layer impedance calculation also considers these parameters in the same way. It is impossible to completely match the input impedance of 50Ω and the output 75Ω, as long as the integrity of the signal and timing issues can be guaranteed.
Question: In the EMC test, the harmonics of the clock signal are found to be very serious. In addition to connecting decoupling capacitors to the power pins in the PCB design, what aspects should be paid attention to to suppress electromagnetic radiation?

Answer: You can put the clock signal on the inner layer, or connect a small capacitor to the ground on the clock line (of course it will affect the clock edge rate).
Vias and pads
a. Vias can only be holed on the inner wall (unless it is marked or the outer diameter is smaller than the inner diameter, the manufacturer will consider it to be non-porous); and the pad can be directly non-pored (the plated in the Advanced of the pad is removed as a non-hole change).

b. The via hole is between the two selected layers. The aperture cannot be 0. For multi-layer boards, through holes, blind holes, buried holes, etc. can be made; and the pads can only be in a single layer (through hole shape). The pad can also be considered in a single MultiLayer layer), the hole diameter can be 0, and the drill hole can only be a through hole.
c. The vias of the same network as the copper-clad will be directly covered when the copper is covered (the same network is selected); and the pads of the same network as the copper-clad can be connected in an optional way.
d. Vias can only be round; and pads can be square, rectangular, octagonal, round, oval, etc., and Pad Stack can be used to define the respective sizes and shapes of the top, middle and bottom layers.

Reliability Design of Printed Circuit Board-Decoupling Capacitor Configuration
In the DC power supply loop, the change of the load will cause the power supply noise. For example, in digital circuits, when the circuit changes from one state to another, a large spike current will be generated on the power line, forming a transient noise voltage. The configuration of decoupling capacitors can suppress the noise generated by load changes, which is a common practice in the reliability design of printed circuit boards. The configuration principles are as follows:
.Connect a 10-100uF electrolytic capacitor across the power input. If the location of the printed circuit board allows, the anti-interference effect of using an electrolytic capacitor above 100uF will be better.

. Configure a 0.01uF ceramic capacitor for each integrated circuit chip. If the printed circuit board space is small and cannot be installed, a 1-10uF tantalum electrolytic capacitor can be configured for every 4-10 chips. The high-frequency impedance of this device is particularly small, and the impedance is less than 1Ω in the range of 500kHz-20MHz. And the leakage current is very small (less than 0.5uA).
.For devices with weak noise capability and large current changes during turn-off, and storage devices such as ROM and RAM, a decoupling capacitor should be directly connected between the power line (Vcc) and ground (GND) of the chip.
.Leads of decoupling capacitors cannot be too long, especially high-frequency bypass capacitors.