PCB Technical - Precautions for designing high-speed PCB circuit boards

Precautions for designing high-speed PCB circuit boards
The number of stacks:
A good laminated structure is the best preventive measure for most signal integrity problems and emc problems, and it is also the most misunderstood by people. There are several factors at play here, and a good way to solve one problem may worsen other problems. Many system design vendors will suggest that there should be at least one continuous plane in the circuit board to control the characteristic impedance and signal quality. As long as the cost is affordable, this is a good suggestion. EMC consultants often recommend placing a ground fill or ground layer on the outer layer to control electromagnetic radiation and sensitivity to electromagnetic interference. This is also a good suggestion under certain conditions. Analyzing signal problems in laminated structures with capacitance models However, due to transient currents, this method may be troublesome in some common designs. First, let's look at the simple case of a pair of power plane/ground plane: it can be seen as a capacitor. It can be considered that the power layer and the ground layer are the two plates of the capacitor. To get a larger capacitance value, you need to move the two plates closer together (distance D) and increase the dielectric constant (ε▼r▼). The larger the capacitance, the lower the impedance, which is what we want because it can suppress noise. No matter how the other layers are arranged, the main power layer and ground layer should be adjacent and in the middle of the stack. If the distance between the power layer and the ground layer is large, it will cause a large current loop and bring a lot of noise. For an 8-layer board, putting the power layer on one side and the ground layer on the other side will cause the following problems

1. Maximum crosstalk. Due to the increase of the mutual capacitance, the crosstalk between the signal layers is greater than the crosstalk of the layers themselves.
2. The largest circulation. Current flows around each power plane and parallel to the signal, a large amount of current enters the main power plane and returns through the ground plane. The EMC characteristics will deteriorate due to the increase of the circulating current.
3. Loss of control over impedance. The farther the signal is from the control layer, the lower the accuracy of impedance control due to other conductors around it.
4. Since it is easy to cause solder short circuit, it may increase the cost of the product.
Characteristic impedance:
We must make a compromise choice between performance and cost. For this reason, I am here to talk about how to arrange digital circuit boards to obtain the best SI and EMC characteristics. The distribution of each layer of the PCB is generally symmetrical. In my humble opinion, more than two signal layers should not be placed next to each other; otherwise, the control over SI will be largely lost. It is best to place the internal signal layers symmetrically in pairs. Unless some signals need to be wired to smt devices, we should minimize the outer signal wiring. The first step of a good design scheme is to correctly design the laminated structure for a circuit board with a large number of layers. We can repeat this placement method many times. You can also add additional power layer and ground layer; just make sure that there is no pair of signal layers between the two power layers. High-speed signal wiring should be arranged in the same pair of signal layers; unless it is encountered due to the connection of SMT devices, this principle must not be violated. All traces of a signal should have a common return path (that is, the ground plane). There are two ideas and methods to judge what two layers can be regarded as a pair:
1. Ensure that the return signals are exactly the same at equal distances. This means that the signals should be routed symmetrically on both sides of the internal ground plane. The advantage of this is that it is easy to control the impedance and circulating current; the disadvantage is that there are many vias on the ground layer, and there are some useless layers.
2. Two signal layers of adjacent wiring. The advantage is that the vias in the ground layer can be controlled to a minimum (using buried vias); the disadvantage is that the effectiveness of this method is reduced for some key signals.
I like to use the second method. It is preferable that the ground connection for element driving and receiving signals can be directly connected to the layer adjacent to the signal wiring layer. As a simple wiring principle, the surface wiring width in inches should be less than one-third of the drive rise time in nanoseconds (for example: high-speed TTL wiring width is 1 inch). If it is powered by multiple power supplies, a ground layer must be laid between the power supply wires to separate them. Do not form a capacitor, so as not to cause AC coupling between the power supplies. The above-mentioned measures are all in order to reduce the circulation and crosstalk, and strengthen the impedance control ability. The ground plane will also form an effective EMC "shielding box". Under the premise of considering the influence on the characteristic impedance, the unused surface area can be made into a ground layer. Characteristic impedance A good laminated structure can effectively control the impedance, and its traces can form an easy-to-understand and predictable transmission line structure. On-site solution tools can handle such problems well, as long as the number of variables is controlled to a minimum, quite accurate results can be obtained. However, when three or more signals are stacked together, this is not necessarily the case, and the reason is subtle. The target impedance value depends on the process technology of the device. High-speed CMOS technology can generally reach about 70 Ω; high-speed TTL devices generally can reach about 80 Ω to 100 Ω. Because the impedance value usually has a great influence on noise tolerance and signal switching, it is necessary to be very careful when choosing impedance; the product manual should give guidance on this. The initial results of the on-site resolution tool may encounter two kinds of problems. The first is the problem of restricted view. The field solution tool only analyzes the influence of nearby traces, and does not consider non-parallel traces on other layers that affect impedance. The on-site solution tool cannot know the details before wiring, that is, when assigning the trace width, but the above-mentioned pair arrangement method can minimize this problem.
It is worth mentioning the influence of partial power planes. The outer circuit board is often crowded with grounded copper wires after wiring, which is beneficial to suppress EMI and balance plating.