PCB Technical - High-speed PCB controllability and electromagnetic compatibility design

(1) Challenges faced by electronic system design

With the large-scale increase in system design complexity and integration, electronic system designers are engaged in circuit design above 100MHZ, and the operating frequency of the bus has reached or exceeded 50MHZ, and some even exceeded 100MHZ. At present, about 50% of the designs have a clock frequency of more than 50MHz, and nearly 20% of the designs have a clock frequency of more than 120MHz.

When the system works at 50MHz, there will be transmission line effects and signal integrity problems; when the system clock reaches 120MHz, unless high-speed circuit design knowledge is used, PCBs designed based on traditional methods will not work. Therefore, high-speed circuit design technology has become a design method that electronic system designers must adopt. The controllability of the design process can only be achieved by using the design techniques of high-speed circuit designers.

(2) What is a high-speed circuit

It is generally believed that if the frequency of a digital logic circuit reaches or exceeds 45MHZ~50MHZ, and the circuit working above this frequency has taken up a certain share of the entire electronic system (for example, 1/3), it is called a high-speed circuit.

In fact, the harmonic frequency of the signal edge is higher than the frequency of the signal itself. It is the rising and falling edges of the signal (or signal jumps) that cause unexpected results in signal transmission. Therefore, it is generally agreed that if the line propagation delay is greater than 1/2 of the rise time of the digital signal driving end, such signals are considered to be high-speed signals and produce transmission line effects.

The transmission of the signal occurs at the instant when the signal state changes, such as the rise or fall time. The signal passes a fixed period of time from the driving end to the receiving end. If the transmission time is less than 1/2 of the rise or fall time, the reflected signal from the receiving end will reach the driving end before the signal changes state. Conversely, the reflected signal will reach the drive end after the signal changes state. If the reflected signal is strong, the superimposed waveform may change the logic state.

(3) Determination of high-speed signals

Above we have defined the preconditions for the occurrence of transmission line effects, but how do we know whether the line delay is greater than 1/2 the signal rise time of the drive end? Generally, the typical value of the signal rise time can be given in the device manual, and the signal propagation time is determined by the actual wiring length in the PCB design. The following figure shows the corresponding relationship between the signal rise time and the allowable wiring length (delay).

The delay per unit inch on the PCB is 0.167ns. However, if there are many vias, many device pins, and many constraints set on the network cable, the delay will increase. Generally, the signal rise time of high-speed logic devices is about 0.2ns. If there are GaAs chips on the board, the maximum wiring length is 7.62mm.

Let Tr be the signal rise time and Tpd be the signal line propagation delay. If Tr≥4Tpd, the signal falls in a safe area. If 2Tpd≥Tr≥4Tpd, the signal falls in the uncertainty region. If Tr≤2Tpd, the signal falls in the problem area. For signals falling in uncertain areas and problem areas, high-speed wiring methods should be used.

(4) What is a transmission line

The traces on thePCB boardcan be equivalent to the series and parallel capacitance, resistance and inductance structures shown in the figure below. The typical value of series resistance is 0.25-0.55 ohms/foot. Because of the insulating layer, the resistance of parallel resistance is usually very high. After adding parasitic resistance, capacitance and inductance to the actual PCB wiring, the final impedance on the wiring is called the characteristic impedance Zo. The wider the wire diameter, the closer to the power/ground, or the higher the dielectric constant of the isolation layer, the smaller the characteristic impedance. If the impedance of the transmission line and the receiving end do not match, the output current signal and the final stable state of the signal will be different, which causes the signal to be reflected at the receiving end, and this reflected signal will be transmitted back to the signal transmitting end and reflected back again. As the energy decreases, the amplitude of the reflected signal will decrease until the voltage and current of the signal stabilize. This effect is called oscillation, and the oscillation of a signal can often be seen on the rising and falling edges of the signal.

(5) Transmission line effect

Based on the above-defined transmission line model, to sum up, the transmission line will bring the following effects to the entire circuit design.

• Reflected signals

• Delay & Timing errors

• Repeatedly crossing the logic level threshold error False Switching

• Overshoot/Undershoot

• Induced Noise (or crosstalk)

• EMI radiation

5.1 Reflected signal

If a trace is not properly terminated (terminal matching), then the signal pulse from the driving end is reflected at the receiving end, causing unexpected effects and distorting the signal profile. When the distortion is very significant, it can cause a variety of errors and cause design failure. At the same time, the susceptibility of the distorted signal to noise increases, which can also cause design failure. If the above situation is not considered enough, EMI will increase significantly, which will not only affect the results of its own design, but also cause the failure of the entire system.

The main reasons for reflected signals are: too long traces; transmission lines that are not terminated by matching, excessive capacitance or inductance, and impedance mismatch.

5.2 Delay and timing errors

Signal delay and timing errors are manifested as: the signal does not jump for a period of time when the signal changes between the high and low thresholds of the logic level. Excessive signal delay may cause timing errors and confusion of device functions.

Problems usually arise when there are multiple receivers. The circuit designer must determine the worst-case time delay to ensure the correctness of the design. The reason for the signal delay: the driver is overloaded, and the wiring is too long.

5.3 Multiple times of crossing the logic level threshold error

The signal may cross the logic level threshold many times during the transition process, resulting in this type of error. The error of crossing the logic level threshold multiple times is a special form of signal oscillation, that is, the oscillation of the signal occurs near the logic level threshold, and crossing the logic level threshold multiple times will cause the logic function disorder. Causes of reflected signals: long traces, unterminated transmission lines, excessive capacitance or inductance, and impedance mismatch.

5.4 Overshoot and undershoot

Overshoot and undershoot come from two reasons: the trace is too long or the signal changes too fast. Although most component receiving ends are protected by input protection diodes, sometimes these overshoot levels will far exceed the component power supply voltage range and damage components.

5.5 Crosstalk

Crosstalk is manifested as when a signal passes through a signal line, the relevant signal will be induced on the signal line adjacent to it on the PCB. We call it crosstalk.

The closer the signal line is to the ground, the greater the line spacing, and the smaller the crosstalk signal generated. Asynchronous signals and clock signals are more prone to crosstalk. Therefore, the method of crosstalk is to remove the crosstalk signal or shield the signal that is seriously interfered.

5.6 Electromagnetic radiation

EMI (Electro-Magnetic Interference) refers to electromagnetic interference. The problems caused include excessive electromagnetic radiation and susceptibility to electromagnetic radiation. EMI is manifested in that when a digital system is powered on, it will radiate electromagnetic waves to the surrounding environment, thereby interfering with the normal operation of electronic equipment in the surrounding environment. The main reason for it is that the operating frequency of the circuit is too high and the layout is unreasonable. There are software tools for EMI simulation, but EMI simulators are very expensive, and it is difficult to set simulation parameters and boundary conditions, which will directly affect the accuracy and practicability of the simulation results. The most common approach is to apply the various design rules for controlling EMI in every aspect of the design, so as to realize the rule-driven and control in every aspect of the design.

(6) Methods to avoid transmission line effects

In view of the influences introduced by the above transmission line problems, let's talk about the methods to control these influences from the following aspects.

6.1 Strictly control the length of key network cables

If there is a high-speed transition edge in the design, the problem of the transmission line effect on the PCB must be considered. Fast integrated circuit chips with very high clock frequencies that are commonly used nowadays have such problems. There are some basic principles to solve this problem: if CMOS or TTL circuits are used for design, the operating frequency is less than 10MHz, and the wiring length should not be greater than 7 inches. The wiring length should not be greater than 1.5 inches at 50MHz. If the operating frequency reaches or exceeds 75MHz, the wiring length should be 1 inch. The maximum wiring length for GaAs chips should be 0.3 inches. If this standard is exceeded, there will be transmission line problems.

6.2 Reasonably plan the topology of the wiring

Another way to solve the transmission line effect is to select the correct wiring path and terminal topology. The topological structure of the wiring refers to the wiring sequence and wiring structure of a network cable. When using high-speed logic devices, unless the length of the trace branch is kept short, signals with rapidly changing edges will be distorted by the branch traces on the signal trunk trace. Under normal circumstances, PCB routing uses two basic topologies, namely Daisy Chain routing and Star distribution.

For daisy chain wiring, the wiring starts from the driving end and reaches each receiving end in turn. If a series resistance is used to change the signal characteristics, the position of the series resistance should be close to the drive end. In terms of controlling the high-order harmonic interference of the wiring, the daisy chain wiring has the best effect. However, this wiring method has the lowest distribution rate, and it is not easy to distribute 100%. In the actual design, we make the branch length in the daisy chain wiring as short as possible. The safe length value should be: Stub Delay <= Trt *0.1.

For example, the length of the branch end in a high-speed TTL circuit should be less than 1.5 inches. This topology occupies less wiring space and can be terminated with a single resistor. However, this wiring structure makes the reception of signals at different signal receiving ends asynchronous.

The star topology structure can effectively avoid the asynchronous problem of the clock signal, but it is very difficult to manually complete the wiring on the high-density PCB board. Using an automatic router is the best way to complete star wiring. Terminating resistors are required on each branch. The resistance of the terminal resistor should match the characteristic impedance of the connection. This can be calculated manually or by CAD tools to calculate the characteristic impedance value and the terminal matching resistance value.

In the above two examples, simple terminal resistors are used. In practice, more complex matching terminals can be selected. The first option is RC matching terminal. The RC matching terminal can reduce power consumption, but it can only be used when the signal is relatively stable. This method is most suitable for matching the clock line signal. The disadvantage is that the capacitance in the RC matching terminal may affect the shape and propagation speed of the signal.

The series resistance matching terminal will not produce additional power consumption, but will slow down the signal transmission. This method is used for bus drive circuits where the time delay has little effect. The advantage of the series resistance matching terminal is that it can reduce the number of on-board devices and the density of wiring.

The last method is to separate the matching terminal. In this way, the matching component needs to be placed near the receiving end. The advantage is that it will not pull down the signal, and noise can be avoided very well. Typically used for TTL input signals (ACT, HCT, FAST).

In addition, the package type and installation type of the terminal matching resistor must also be considered. Generally, SMD surface mount resistors have lower inductance than through-hole components, so SMD packaged components become the first choice. If you choose ordinary in-line resistors, there are also two options for installation: vertical and horizontal.

In the vertical installation mode, one mounting pin of the resistor is very short, which can reduce the thermal resistance between the resistor and the circuit board, so that the heat of the resistor can be more easily dissipated into the air. But a longer vertical installation will increase the inductance of the resistor. Horizontal installation has lower inductance due to lower installation. However, the overheated resistance will drift. In the worst case, the resistance will become an open circuit, causing the PCB trace termination matching failure and becoming a potential failure factor.

6.3 Methods to suppress electromagnetic interference

A good solution to the signal integrity problem will improve the electromagnetic compatibility (EMC) of the PCB board. One of the very important is to ensure that the PCB board has a good grounding. It is very effective to use a signal layer with a ground layer for complex designs. In addition, minimizing the signal density of the outermost layer of the circuit board is also a good way to reduce electromagnetic radiation. This method can be realized by using the "surface area layer" technology "Build-up" design and manufacturing PCB. The surface area layer is realized by adding a combination of a thin insulating layer and micro-holes used to penetrate these layers on a common process PCB. The resistance and capacitance can be buried under the surface layer, and the trace density per unit area will be nearly doubled. Reduce the size of the PCB. The reduction of PCB area has a huge impact on the topological structure of the trace, which means that the current loop is reduced, the length of the branch trace is reduced, and the electromagnetic radiation is approximately proportional to the area of the current loop; at the same time, the small size feature means high-density lead Foot-packaged devices can be used, which in turn reduces the length of the wire, thereby reducing the current loop and improving the electromagnetic compatibility characteristics.

6.4 Other applicable technologies

In order to reduce the instantaneous overshoot of the voltage on the power supply of the integrated circuit chip, a decoupling capacitor should be added to the integrated circuit chip. This can effectively remove the effects of burrs on the power supply and reduce the radiation of the power loop on the printed board.

When the decoupling capacitor is directly connected to the power tube leg of the integrated circuit instead of the power layer, the effect of smoothing the burr is best. This is why some device sockets have decoupling capacitors, and some devices require the distance between the decoupling capacitor and the device to be small enough.

Any high-speed and high-power devices should be placed together as much as possible to reduce the transient overshoot of the power supply voltage.

If there is no power layer, the long power connection will form a loop between the signal and the loop, becoming a radiation source and a sensitive circuit.

The situation where the traces form a loop that does not cross the same network cable or other traces is called an open loop. If the loop passes through other wires of the same network cable, it constitutes a closed loop. In both cases, antenna effects (wire antennas and loop antennas) are formed. The antenna generates EMI radiation externally and is also a sensitive circuit itself. The closed loop is a problem that must be considered, because the radiation it generates is approximately proportional to the closed loop area.

Concluding remarks

High-speed circuit design is a very complicated design process. ZUKEN's high-speed circuit routing algorithm (Route Editor) and EMC/EMI analysis software (INCASES, Hot-Stage) are used to analyze and find problems. The method described in this article is specifically aimed at solving these high-speed circuit design problems. In addition, there are multiple factors that need to be considered when designing high-speed circuits, and these factors are sometimes opposed to each other. For example, when high-speed devices are placed close to each other, although the delay can be reduced, crosstalk and significant thermal effects may occur. Therefore, in the design, it is necessary to weigh various factors and make a comprehensive compromise; not only meet the design requirements, but also reduce the design complexity. The use of high-speed PCB design methods constitutes the controllability of the design process, and only controllable ones are reliable.