PCB Blog - Crosstalk Problems in High Speed PCB Board Design

This article will analyze the causes of signal crosstalk in high-speed PCB board design, as well as the methods to suppress and improve. In today's rapidly developing electronic design field, high speed and miniaturization have become the inevitable trend of design. At the same time, factors such as the increase of signal frequency, the reduction of the size of the circuit board, the increase of the wiring density, and the reduction of the interlayer thickness caused by the increase of the number of board layers will cause various signal integrity problems. Therefore, it is necessary to consider the signal integrity problem when designing the high-speed board, master the theory of signal integrity, and then guide and verify the design of the high-speed PCB board. Among all signal integrity problems, crosstalk is very common. Crosstalk can occur inside chips, as well as on circuit boards, connectors, chip packages, and cables.

1. The generation of PCB board crosstalk

Crosstalk refers to the influence on adjacent transmission lines due to electromagnetic coupling when a signal is transmitted on a transmission channel. Excessive crosstalk may cause false triggering of the circuit, resulting in the system not working properly. A changing signal (such as a step signal) propagates from A to B along the transmission line, and a coupled signal occurs on the transmission line C to D. When the changing signal returns to a stable DC level, the coupled signal also ceases to exist. Therefore, crosstalk only occurs in the process of signal hopping, and the faster the signal changes, the greater the crosstalk generated. Crosstalk can be divided into capacitive coupling crosstalk (due to the voltage change of the interference source, induced current is induced on the object to be interfered, resulting in electromagnetic interference) and inductive coupling crosstalk (due to the current change of the interference source, induced voltage is caused on the object to be interfered, thereby causing electromagnetic interference. cause electromagnetic interference). Among them, the crosstalk signal generated by the coupling capacitor can be divided into forward crosstalk and reverse crosstalk Sc on the victim network, and these two signals have the same polarity; the crosstalk signal generated by the coupled inductor is also divided into forward crosstalk and reverse crosstalk Sc, The two signals have opposite polarities. Both mutual capacitance and mutual inductance are related to crosstalk, but need to be considered separately. When the return path is a wide, uniform plane, like most coupled transmission lines on a circuit board, the amount of capacitive and inductive coupling currents is about the same. At this time, it is necessary to predict the amount of crosstalk between the two. If the medium of the parallel signal is fixed, that is, in the case of a stripline, then the forward crosstalk caused by the coupled inductance and capacitance is approximately equal and cancels each other out, so it is only necessary to consider the reverse crosstalk. If the medium of the parallel signal is not fixed, that is, in the case of a microstrip line, the forward crosstalk caused by the coupling inductance is greater than the forward crosstalk caused by the coupling capacitance with the increase of the parallel length, so the crosstalk of the inner parallel signal is higher than that of the surface layer. The crosstalk of parallel signals is small.

2. Analysis and suppression of PCB crosstalk

The whole process of high-speed PCB board design includes steps such as circuit design, chip selection, schematic design, PCB board layout and wiring. During design, it is necessary to find crosstalk in different steps and take measures to suppress it to achieve the purpose of reducing interference. .

3. Calculation of PCB crosstalk

The calculation of crosstalk is very difficult. There are three main factors that affect the amplitude of the crosstalk signal: the degree of coupling between traces, the spacing of traces, and the termination of traces. The current distribution along the microstrip traces on the forward and return paths is shown in Figure 2. The current distribution between traces and planes (or between traces and traces) is co-impedance, which will result in mutual coupling due to current spreading, with peak current density directly below the center of the trace and from the trace Both sides of the decay rapidly towards the ground. When the traces are far apart from the plane, the loop area between the forward and return paths increases, increasing the circuit inductance proportional to the loop area. The following equation describes the current distribution inducting the entire loop formed by the forward and return current paths. The current it describes is also the total energy stored in the magnetic field around the signal trace.

4. Analysis of PCB crosstalk

Using EDA tools to simulate the crosstalk of the PCB board can quickly find, locate and solve the crosstalk problem in the PCB board implementation. Simulation in high-speed design includes schematic simulation before routing and PCB board simulation after routing. It can use the constraints obtained by simulation as actual routing constraints to predict and eliminate crosstalk problems earlier, thereby effectively constraining layout and changes Stack up and optimize clocking, critical signal topology and termination prior to board layout. BoardSim is for post-placement and routing simulation, it can predict unknown coupling effects between PCB board wires, display the simulation results in an oscilloscope, and display the detailed details of all crosstalk waveforms. Its purpose is to predict and discover the crosstalk problem of the actual finished product, thereby saving the designer's time and avoiding the repeated design and manufacture of the principle prototype. For pre-layout simulation, LineSim needs to establish a basic coupling model first, and set different constraints for different circuit environments, including wire spacing, parallel length, switching speed of driver IC, medium thickness, stack structure, etc. . These constraints allow designers to understand where problems may arise early in the design, so as to plan effectively, reduce crosstalk that may occur before placement and routing, and find constraints as constraints for the next step of placement and routing. In terms of driver chip selection, IBIS (Input/Output Buffer Information Specification) model can be introduced, which is generally provided by chip manufacturers. When using BoardSim to perform crosstalk analysis on wiring, there are three ways: interactive crosstalk simulation, fast batch processing and detailed batch processing. Among them, the interactive crosstalk simulation can visually observe the interference situation through the digital oscilloscope. The concepts of geometric threshold and electrical threshold are presented here. The geometric threshold will define a certain area, and any network that enters this area and has a certain length is considered to be an attack network; the electrical threshold will define an interference amount, and any network that causes interference to the network beyond this amount is considered an attack. network. The use of geometric thresholds requires the designer to have a certain understanding of crosstalk, and to know how much crosstalk will be generated at what distance and at which layer. Therefore, it is generally recommended to use electrical thresholds, which are more accurate and faster to analyze. The basic model has two networks: the driver A0 (the driving line is the clock signal line, and its operating frequency is 5.12MSPS), which is connected to the 1MW resistor C0 through the transmission line; the driver A1 in the receiving mode is connected to the 720KW resistor C1 through the transmission line. superior. The characteristic impedance of each coupled transmission line is 68.8W, and the coupling length is 9in. HyperLynx calculates the delay per line to be approximately 1.581ns. The model is divided into 8 layers, and the two signal lines are set as inner layer lines (and microstrip lines) and are on the same layer. In the PCB layout and routing constraints, the line width is 5mil, the line spacing is 5mil, and the relative permittivity is set to 4.3. In the figure, oscilloscope probes are added at A0, B1, and C1 respectively. The oscilloscope can be used to view the waveform. The 10MW resistance of B1 is also set for adding probes.

5. Crosstalk suppression

Whether it is the crosstalk calculation before design, the simulation before layout and routing, or the simulation after layout and routing, it is all to make the PCB board can quickly reach the interference. Therefore, it is necessary to use previous experience in the design process to solve the current problem. The following is a summary of experience to effectively avoid crosstalk in layout and routing:

1) The crosstalk generated by capacitive coupling and inductive coupling increases with the increase of the load impedance of the interfered line, so reducing the load can reduce the influence of coupling interference;

2) Try to increase the distance between the capacitive coupling wires that may occur, and it is more effective to isolate the wires with a ground wire;

3) Inserting a ground wire between adjacent signal wires can also effectively reduce capacitive crosstalk. This ground wire needs to be connected to the ground layer every 1/4 wavelength.

4) It is difficult to suppress inductive coupling. It is necessary to reduce the number of loops as much as possible, reduce the loop area, and do not let the signal loops share the same wire.

5) Avoid signal sharing loops.

In the process of high-speed PCB board design, not only a detailed understanding of theoretical concepts is required, but also continuous accumulation of experience and continuous improvement of the theory. At the same time, the proficient use of relevant auxiliary software can also shorten the design cycle, thereby improving competitiveness, and playing an important role in the successful completion of the design. High-speed PCB board-level and system-level design is a complex process, and signal integrity issues including signal crosstalk cannot be ignored. Use different methods at various stages of the design cycle to ensure designs are completed quickly and efficiently, saving time and avoiding duplication on PCB board.