PCB Blog - PCB board testing and design procedures

As miniaturization continues to increase, PCB board of component and wiring technologies have also undergone tremendous advances, such as highly integrated miniature ICs packaged in BGA housings, and the insulation spacing between conductors has been reduced to 0.5mm, to name just two examples. The wiring design method of electronic components has an increasing influence on whether the test in the future production process can be carried out well. Here are a few important rules and helpful tips. By following certain procedures (DFT-Design for Testability, Design for Testability), the cost of preparing and implementing production tests can be greatly reduced. These procedures have been developed over the years and, of course, they have to be expanded and adapted accordingly if new production and component technologies are introduced. As the structure of electronic products becomes smaller and smaller, there are two particularly striking problems: one is that there are fewer and fewer circuit nodes that can be contacted; the other is that methods such as In-Circuit-Test Apps are restricted. In order to solve these problems, corresponding measures can be taken in circuit layout, and new test methods and innovative adapter solutions can be adopted. The solution to the second problem also involves making additional tasks for the test system that was originally used as a stand-alone process. These tasks include programming memory components through test systems or implementing integrated component self-tests (Built-in Self Test, BIST, built-in self-test). Moving these steps into the test system, on the whole, creates more added value. In order to implement these measures smoothly, corresponding considerations must be taken in the stage of product research and development.

1. What is testability

The meaning of testability can be understood as: test engineers can use the simplest method to detect the characteristics of a certain component to see if it can meet the expected function. Simply put:

How simplistic is the method of testing whether a product meets technical specifications?

How fast can you write a test program?

How comprehensive is the discovery of product failures?

How simple is the method of accessing test points?

Mechanical and electrical design practices must be considered in order to achieve good testability. Of course, to achieve testability, there is a price to pay, but it has a series of benefits for the entire process, so it is an important prerequisite for the successful production of products.

2. Why develop test-friendly techniques

In the past, if a product could not be tested at the previous test point, the problem was simply pushed to one test point. If a product defect cannot be found during production testing, the identification and diagnosis of the defect is simply moved to functional and system testing. On the contrary, today people try to find defects as early as possible, and its benefits are not only low cost, but more importantly, today's products are very complex, and some manufacturing defects may not be detected at all in functional testing. For example, for some components to be pre-installed software or programming, there is such a problem. (such as flash memory or ISPs: In-System Programmable Devices). The programming of these components must be planned during the development phase, and the test system must master this programming. Testing friendly circuit designs cost some money, however, testing difficult circuit designs costs more. The test itself has a cost, and the test cost increases with the increase of the test series; from online tests to functional tests and system tests, the test cost is increasing. Skipping one of the tests would cost even more. The general rule is to increase the cost of each test by a factor of 10. With a test-friendly circuit design, faults can be detected early so that the money spent on a test-friendly circuit design can be quickly compensated.

3. How documentation affects testability

Only by taking full advantage of the complete data in component development is it possible to develop a test program that can fully detect faults. In many cases, close cooperation between development and testing is necessary. Documentation has an indisputable impact on test engineers' understanding of component functionality and development test strategies. To circumvent the problems created by lack of documentation and poor understanding of component functionality, test system manufacturers can rely on software tools that automatically generate test patterns on a random basis, or rely on non-vector methods, which only count as an expedient solution. The complete documentation before testing includes a parts list, circuit design data (mainly CAD data), and details about the function of service components (such as data sheets). With all the information in hand, it is possible to compile test vectors, define component failure patterns or perform certain pre-adjustments. Certain mechanical data are also important, such as those needed to check components for good soldering and alignment. , For programmable components, such as flash memory, PLD, FPGA, etc., if they are not programmed during installation, they should be programmed on the test system, and their programming data must also be known. The programming data for the flash device should be complete. If the flash chip contains 16Mbit data, it should be able to use 16Mbit, which can prevent misunderstanding and avoid addressing conflict. This may occur, for example, if a 4Mbit memory is used to provide only 300Kbit of data to a component. Of course, the data should be prepared into a popular standard format, such as Intel's Hex or Motorola's S-record structure. Most test systems can interpret these formats as long as they can program flash or ISP components. Much of the information previously mentioned, many of which is also required for component fabrication. Of course, a clear distinction should be made between manufacturability and testability, as these are entirely different concepts and thus constitute different premises.

4. Mechanical contact conditions for good testability

Even circuits with very good electrical testability can be difficult to test without considering the ground rules of mechanics. Many factors limit electrical testability. If the test points are not enough or too small, it is difficult for the probe bed adapter to reach every node of the circuit. If the test point position error and size error are too large, there will be a problem of poor test repeatability. When using the probe bed adapter, a series of recommendations regarding the size and positioning of the latch holes and test points should be observed.

5. Electrical prerequisites for testability

Electrical prerequisites are as important to good testability as mechanical contact conditions, and both are essential. A gate circuit cannot be tested. The reason may be that the start input terminal cannot be contacted through the test point, or the start input terminal is in the package and cannot be contacted from the outside. In principle, both cases are not good. make the test impossible. When designing the circuit, it should be noted that all components to be tested by the online test method should have some mechanism to enable each component to be electrically insulated. This mechanism can be achieved by disabling the input, which controls the output of the element in a static high-ohmic state. Although almost all test systems are capable of back-driving the state of a node to an arbitrary state, the node involved still needs to be equipped with a disabled input, first bringing the node to a high ohmic state, and then The corresponding level is added "gently". Likewise, the beat generator is always disconnected directly from the back of the oscillator via a start lead, gate, or plug-in bridge. The start input should never be connected directly to the circuit but should be connected to the circuit through a 100-ohm resistor. Each component should have its own start, reset or control pins. It must be avoided that the start inputs of many components share a resistor connected to the circuit. This rule also applies to ASIC components, which should also have a lead pin through which the output can be brought to a high ohmic state. It is also very helpful for a tester to initiate a reset if the component can be reset when the operating voltage is turned on. In this case, the component can simply be placed in a specified state prior to testing. Unused component leads should also be accessible, as undiscovered shorts in these places can also cause component failure. In addition, unused gates are often used later for design improvements, and they may be rewired into the circuit. So it is also important that they are tested from the outset to ensure that their artifacts are reliable.

6. About flash memory and other programmable components

Flash memory programming times can sometimes be long (up to 1 minute for large memories or memory banks). Therefore, back-driving of other components is not allowed at this time, otherwise, the flash memory may be damaged. To avoid this, all components connected to the control lines of the address bus must be placed in a high ohmic state. Likewise, the data bus must be able to be isolated to ensure that the flash memory is unloaded and available for further programming. There are some requirements for in-system programmable components (ISPs), products from companies such as Altera, Xilinx, and Lettuce, as well as other special requirements. In addition to the mechanical and electrical prerequisites for testability should be guaranteed, the possibility of programming and validating data is also guaranteed. For Altera and Xilinx components, a serial vector format (Serial VectorFormat SVF) is used, which has recently become an industry standard. Many test systems can program such components and user input data in serial vector format (SVF) to test signal generators. Programming these elements by Boundary-Scan-Kette JTAG also programs the serial data format. When compiling programming data, it is important to take into account the entire chain of components in the circuit and not restore data only to the components to be programmed. When programmed, the automatic test signal generator considers the entire component chain and plugs other components into the bypass model. Instead, Lattice requires data in JEDEC format and is programmed in parallel via the usual inputs and outputs. After programming, the data is also used to check component functionality. The data provided by the development department should be as easy as possible to be used directly by the test system, or by a simple transformation.

7. What should be paid attention to for boundary-scan (JTAG)

Components based on a fine mesh of complex components provide test engineers with few accessible test points. It is still possible to improve testability at this point as well. Boundary-scan and integrated self-test techniques can be used for this to shorten test completion time and improve test results. For development engineers and test engineers, a test strategy based on boundary-scan and integrated self-test techniques will definitely add to the expense. Development engineers must use boundary-scan components (IEEE-1149.1-standard) in the circuit, and try to make the corresponding specific test leads accessible (such as test data input-TDI, test data output-TDO, test clock frequency - TCK, and test mode selection - TMS and ggf. test reset). The test engineer develops a boundary scan model (BSDL - Boundary Scan Description Language) for the component. At this point, he must know what boundary-scan functions and instructions the component support. Boundary-scan testing can diagnose shorts and opens down to the lead level. In addition, if the development engineer has specified, the automatic test of the component can be triggered by the boundary scan command "RunBIST". Especially when there are many ASICs and other complex components in the circuit, there is no customary test model for these components. By using boundary-scan components, the cost of formulating test models can be greatly reduced. The degree of time and cost reduction is different for each element. For a circuit with an IC, if 100% discovery is required, about 400,000 test vectors are needed. By using a boundary scan, the number of test vectors can be reduced to hundreds at the same fault detection rate. Therefore, the boundary scan method is particularly advantageous when there is no test model, or when the nodes touching the circuit are limited. Whether or not to use boundary scans depends on the increased cost of development and manufacturing. Boundary-scan must be weighed against the time required to find faults, test time, time to market, adapter cost, and save as much as possible. In many cases, mixing traditional in-line testing methods with boundary-scan methods is the solution on PCB board.