PCB Blog - Several effective methods for PCB board flying probe test

PCB board flying probe test is one of the methods to check the electrical function of PCB (open and short circuit test). A flying tester is a system for testing PCB boards in a manufacturing environment. Instead of using all the traditional bed-of-nails interfaces found on traditional in-circuit test machines, flying probe testing uses four to eight independently controlled probes that move to the component under test. The unit under test (UUT, unit under test) is transported into the testing machine by belt or other UUT conveying system. Then fixed, the probes of the tester contact the test pads and vias to test the individual components of the unit under test (UUT). Test probes are connected to drivers (signal generators, power supplies, etc.) and sensors (digital multimeters, frequency counters, etc.) through a multiplexing system to test components on the UUT. While one element is being tested, other elements on the UUT are electrically shielded by the prober to prevent reading interference.

The steps of making the flying probe test program:

1)Import the layer file, check, arrange, align, etc., and then rename the two outer layers to frontrear. The inner layer is renamed to ily02, ily03, ily04neg (if it is a negative film), rear, rearmneg.
2)add three layers, respectively copy the two solder mask layers and the drilling layer to the added three layers, and change the name to frommneg, rearmneg, mehole. Blind and buried vias can be named met01-02. , met02-05, met05-06 and so on.
3)Change the D code of the copied frommneg and rearmneg to a round of 8mil. We call the frontneg the front test point and the rearmneg the back test point.
4)delete the NPTH hole, find the via hole according to the line, and define the exception hole.
5)Use fron and mehole as the reference layer, change the fronmneg layer to on, and check to see if the test points are all at the window opening of the front layer circuit. Test points in holes larger than 100 mil are to be moved to the solder ring for testing. The test points at the BGA that are too dense should be misplaced. Some redundant intermediate test points can be appropriately deleted. The back layer operates the same.
6)Copy the sorted test point frommneg to the fron layer, and copy the rearmneg to the rear layer.
7)Activate all layers and move to 10,10mm.
8)The output gerber file is named fron, ily02, ily03, ily04neg, ilyo5neg, rear, frommneg, rearmneg, mehole, met01-02, met02-09, met09-met10 layers. Then use Ediapv software

1) Import all gerber files such as fron, ily02, ily03, ily04neg, ilyo5neg, rear, frommneg, rearmneg, mehole, met01-02, met02-09, met09-met10 layers.

2) Generate the network. net annotation of artwork button.

3) Generate test files. Make test programs button, input the D code of the test hole.

4) Save.
5) Set the reference point and you are done. Then take it to the flying probe machine and test it.
5.1 Using this method to make test files often makes many test points, and the intermediate points cannot be automatically deleted.
5.2 The test of the hole is not well grasped. Looking at the generated connectivity (open) test points in ediapv, there are no test points for individual holes. Another example: there is a line on one side of the hole, but there is no line on the other side. Logically, the hole should be tested on the side without the line. However, the test points generated by ediapv conversion are random, sometimes wrong after right and wrong.
5.3 If there is no window for the REAR surface solder mask, the name of the REAR layer can be named as another name, so that the measurement point will not be inexplicably run out of the EDIAPV on PCB board.