PCB Blog - Design of high speed PCB board based on Cadence

1. The introduction
The corresponding high-speed PCB board is more and more widely used, the design is more and more complex. With the increasing demand for communication, the speed of signal transmission and processing is getting faster and faster. High-speed circuit has two meanings: first, it is high frequency. It is generally believed that the frequency of digital circuit reaches or exceeds 45MHz to 50MHz, and the circuit working at this frequency has accounted for one third of the whole system, so it is called high-speed circuit. In addition, considering the rise and fall time of the signal, when the rise time of the signal is less than 6 times the signal transmission delay, the signal is considered as high-speed signal, which has nothing to do with the specific frequency of the signal.

2. Basic content of high-speed PCB board design
High-speed circuit design in the modern circuit design of the proportion is more and more large, the design is more and more difficult, its solution not only needs high-speed devices, but also needs the designer's wisdom and careful work, must carefully study and analyze the specific situation, to solve the existing high-speed circuit problems. Generally speaking, the design mainly includes three aspects: signal integrity design, electromagnetic compatibility design, power integrity design.

2.1 Signal Integrity design

Signal integrity refers to the quality of the signal on the signal line. A signal with good signal integrity means that it has the voltage level values necessary to achieve when required. Poor signal integrity is not caused by any one factor, but by a combination of factors in the board-level design. Especially in high speed circuit, the switching speed of the chip used is too fast, the arrangement of terminal components is not reasonable, the interconnection of the circuit is not reasonable and so on will cause the signal integrity problem. It mainly includes crosstalk, reflection, overshoot and downshoot, oscillation, signal delay, etc.

2.1.1 Crosstalk (crosstalk)
Crosstalk is the unnecessary coupling between two adjacent signal lines. The mutual inductance and tolerance between signal lines cause the noise on the line. Therefore, it is divided into inductive crosstalk and capacitive crosstalk, which cause coupled current and coupled voltage respectively. Crosstalk should be considered when the edge rate of the signal is below 1ns. If there is alternating signal current through the signal line, it will generate alternating magnetic field, and the adjacent signal line in the magnetic field will induce signal voltage. The parameters of general PCB board layer, the distance between signal lines, the electrical characteristics of the driving end and the receiving end, and the connection mode of signal line all have certain influence on crosstalk. In Cadence signal simulation tool, 6 coupling signal lines can be simulated after crosstalk at the same time. The scanning parameters that can be set are: dielectric constant of PCB board, thickness of medium, thickness of immersed copper, length and width of signal line, spacing of signal line. In the simulation, it is necessary to specify a damaged signal line, that is, to investigate the interference of another signal line to this line, and set the excitation as constant high or constant low, so that the sum of the induced voltage of other signal lines to this signal line can be measured, so that the spacing and parallel length can meet the requirements.

2.1.2 Reflex (reflection)
Reflection is the echo of a signal along a transmission line, as we know when light travels through a discontinuous medium and some of its energy is reflected back. At this point, the signal power is not all transmitted to the load, some is reflected back. In a high-speed PCB, the wire must be equivalent to the transmission line. According to the transmission line theory, if the source and the load have the same impedance, the reflection will not occur. A mismatch in impedance between the two causes reflection, and the load reflects part of the voltage back to the source. The reflected voltage may be positive or negative, depending on the magnitude of the relationship between the load impedance and the source impedance. If the reflected signal is strong and superimposed on the original signal, it is likely to change the logical state, resulting in receiving data errors. If the clock signal may cause the clock along the monotonic, and then cause the wrong trigger. General wiring geometry, incorrect wire terminations, transmission through connectors, and discontinuities in the power plane can all cause such reflections. In addition, there is often an output with multiple receivers, and then the reflection generated by different wiring strategies has different effects on each receiver, so the wiring strategy is also a factor that can not be ignored.

2.1.3 Overshoot and undershoot

Overshoot is a signal jump caused by too fast circuit switching and the reflection mentioned above, that is, the signal peak exceeds the peak or valley value of the set voltage. A downdraft is the next trough or peak. Excessive overshoot can cause the protection diode to work, leading to premature failure, and serious damage to the device. Excessive downruns can cause spurious clock or data errors, which can be reduced or eliminated by adding appropriate endpoints.

2.1.4 Oscillations and Pawnchess
The phenomenon of oscillation is the repeated occurrence of overshot and downshot, signal oscillation and surrounding oscillation is caused by the impedance mismatch between the receiving end and the transmission line and the source end caused by excessive inductance and capacitance on the line, usually occurs near the logic level threshold, crossing the logic level threshold for many times will lead to logic dysfunction. Oscillations and circumferential oscillations are caused by as many factors as reflections, and oscillations can be reduced by appropriate terminating or changing PCB parameters, but cannot be completely eliminated. In Cadence's signal simulation software, the above signal integrity problems are measured in reflection parameters. In the IBIS model driving device and receiving repository, we only need to set up different transmission line impedance parameters, resistance, signal transmission rate or stripline and microstrip line, can be calculated directly by using the simulation tool signal waveform and the corresponding data, so that you can find the matching transmission line impedance value, resistance, signal transmission rate, In the corresponding PCB board software Allegro, the width of the corresponding signal line in each layer can be obtained according to the corresponding transmission line impedance value and signal transmission rate (the order and parameters of lamination need to be set in advance). There are many ways to choose resistance matching, including source end - to - end and parallel end - to - end, etc. In the wiring strategy can also choose different ways: chrysanthemum, star, custom, each way has its advantages and disadvantages, according to different circuit simulation results to determine the specific selection.

2.1.5 Signal Delay
The circuit can only receive data in accordance with the specified time sequence, too long signal delay may lead to confusion of timing and function, in a low-speed system will not be a problem, but the signal edge rate increases, the clock rate increases, the transmission time between devices and synchronization time will be shortened. Drive overload and long wiring will cause delays. All gate delays must be met in shorter and shorter time budgets, including setup time, hold time, line delay and deflection. Because the equivalent capacitance and inductance on the transmission line will delay the digital switching of the signal, coupled with the oscillation winding caused by reflection, the data signal can not meet the time required by the receiving device to receive correctly, resulting in receiving errors. In Cadence signal simulation software, the signal delay is also measured in the reflection sub-parameters, Settledelay, Switchdelay and Propdelay. The first two parameters are related to test load in IBIS model library. These two parameters can be determined by user manual parameters of driver and receiver devices. They can be compared with simulated Settledelay and Switchdelay. If the Switchdelay values obtained in Slow mode are all smaller than the calculated value, and the Switchdelay values obtained in Fast mode are all larger than the calculated value, then the Propdelay range between the two devices we really need can be obtained. During the placement of a specific device, if the device is not in an appropriate position, the part of the corresponding delay table will show red, which will turn blue when the position is adjusted properly, indicating that the delay between the devices has met the Propdelay range specified.

2.2 Design for Electro Magnetic Compatibility
Electromagnetic compatibility includes electromagnetic interference and electromagnetic tolerance, that is, excessive electromagnetic radiation and sensitivity to electromagnetic radiation. There are two kinds of electromagnetic interference: conduction interference and radiation interference. Conducted interference refers to the conduction of signals from one electrical network to another electrical network through conductive medium in the form of current. In PCB board, it is mainly manifested as ground noise and power noise. Radiated interference is when a signal radiates out in the form of electromagnetic waves that affect another electrical network. In the design of high-speed PCB board and system, high frequency signal line, chip pins, connectors and so on May become the radiation interference source with antenna characteristics. According to the importance of EMC design, it can be divided into four levels: device and PCB level design, grounding system design, shielding system design and filtering design. Among them, the first two are important, the device and PCB board level design mainly includes the selection of active devices, circuit board stacking, layout and wiring, etc. The design of grounding system mainly includes grounding mode, ground impedance control, ground loop and shielding layer grounding. In Cadence simulation tool, simulation parameters of electromagnetic interference can be set in the X, Y, Z direction of the distance, frequency range, design allowance, compliance with standards, etc. This simulation belongs to the post-simulation, mainly to check whether it meets the design requirements, therefore, in the preliminary work, we also need to design according to the theory of electromagnetic interference, the usual practice is to control the electromagnetic interference design rules applied to each link of the design, to achieve the rule drive and control in each link.

2.3 Power integrity design
In high-speed circuits, power supply and ground integrity is also a very important factor, because power supply integrity and signal integrity are closely related. In most cases, the main cause of signal distortion is the power supply system. For example: the ground rebound noise is too large, the design of uncoupling capacitor is inappropriate, the multi-power supply or ground plane segmentation is not good, the stratum design is not reasonable, the current distribution is not equal will bring power supply integrity problems, resulting in signal distortion and affect the integrity of the signal. The main ideas to solve the problem are to determine the power distribution system, to divide the large size circuit board into several small size boards, to determine the decoupling capacitance based on the Ground Bounce noise, and to consider the whole PCB board. When they have big current flowing in the circuit to play, such as a large amount of chip output at the same time open, there will be a larger transient current flow in the chip from the power source of the plate plane, chip packages and resistance and inductance of the power plane will cause the power supply noise, it will not produce in the real ground plane voltage fluctuations and changes, the noise will affect the other components of the action. In the design, reducing load capacitance, increasing load resistance, decreasing ground inductance and reducing the number of switches at the same time can reduce ground elastic. Due to geoelectric plane segmentation, for example, the stratum is divided into digital ground, analog ground, shielded ground, etc., when the digital signal goes to the analog ground line region, the ground plane backflow noise will be generated. At the same time, depending on the device selected, the power supply layer may be divided into several different voltage layers, so the ground snap and backflow noise need special attention. The choice of power distribution system and decoupling capacitor is very important in the design of power supply integrity. Generally, keep the impedance between the power supply system (power supply and ground plane) as low as possible. We can determine the target impedance we want to achieve through the specified range of voltage and current changes, and then adjust the relevant factors in the circuit to make the impedance of each part of the power supply system and the target impedance. For the decoupling capacitor, it is necessary to consider the parasitic parameters of the capacitor, quantitatively calculate the number of the decoupling capacitor and the capacitance of each capacitor and the specific location, as far as possible to do not more than one capacitor, not less than one. In Cadence simulation tools, grounding bounce is called Simultaneous switch noise. In the simulation, the parasitic inductance, capacitance and resistance between the power supply and the parasitic inductance, capacitance and resistance of the device package are taken into account, and the results are more consistent with the actual situation. In addition, according to the circuit type and working frequency used by the system, after setting the desired parameters, the appropriate capacitance size and placement position can be calculated, and a grounding loop with low impedance can be designed to solve the problem of power supply integrity on PCB board.