PCB News - Stack-up issues in high-speed PCB design

With the continuous emergence of high-speed circuits, the complexity of PCB boards is getting higher and higher. In order to avoid interference from electrical factors, the signal layer and power layer must be separated, so the design of multi-layer PCBs is involved. In the design of multi-layer boards, the arrangement of the layers is particularly important. A good stack design will greatly reduce the impact of EMI and crosstalk. In the following discussion, we will specifically analyze how stack design affects the electrical performance of high-speed circuits.

one. Multilayer board and copper layer (Plane)
Compared with ordinary PCB boards in the design of multi-layer boards, in addition to adding the necessary signal wiring layers, the most important thing is to arrange independent power and ground layers (copper layers). In high-speed digital circuit systems, the advantages of using power and ground to replace the previous power and ground buses are mainly:
Provide a stable reference voltage for the conversion of digital signals.
Evenly apply power to each logic device at the same time
Effectively suppress crosstalk between signals
The reason is that the use of a large area of copper as the power supply and ground layer greatly reduces the resistance between the power supply and the ground, so that the voltage on the power layer is very uniform and stable, and it can ensure that each signal line has a close ground plane corresponding to it. At the same time, the characteristic impedance of the signal line is reduced, which is also very beneficial for effectively reducing crosstalk. Therefore, for some high-end high-speed circuit designs, it has been clearly stipulated that a 6-layer (or more) stacking solution must be used, such as Intel's requirements for PC133 memory module PCB boards. This is mainly considering the electrical characteristics of the multilayer board, as well as the suppression of electromagnetic radiation, and even the ability to resist physical and mechanical damage is significantly better than the low-layer PCB board.
If you consider the cost factor, it is not that the more layers the more expensive the price, because the cost of the PCB board is not only related to the number of layers, but also related to the density of the wiring per unit area. After reducing the number of layers, the wiring The space will inevitably be reduced, thereby increasing the density of the traces, and even the design requirements have to be reduced by reducing the line width and shortening the spacing. Often the cost increase caused by these may exceed the cost reduction by reducing the stack. Coupled with the deterioration of electrical performance, this approach is often counterproductive. Therefore, for designers, all aspects must be considered.

two. The influence of the ground plane layer on the signal under high frequency
If we take the PCB microstrip wiring as a transmission line model, then the ground plane layer can also be regarded as a part of the transmission line. Here, the concept of "loop" can be used to replace the concept of "ground". The ground copper layer is actually a signal The return path of the line. The power layer and the ground layer are connected by a large number of decoupling capacitors. In the case of AC, the power layer and the ground layer can be regarded as equivalent. What is the difference between the current loop at low frequency and high frequency? From the figure below, we can see that at low frequency, the current flows back along the path with the smallest resistance, while at high frequency, the current is along the smallest inductance. The loop flow back is also the path with the least impedance, and the loop current is concentrated and distributed directly under the signal trace.

At high frequencies, when a wire is directly arranged on the ground layer, even if there is a shorter loop, the loop current must flow directly from the wiring layer under the originating signal path back to the signal source. This path has the smallest impedance, that is, inductance. The smallest and largest capacitance. This method of suppressing the electric field by large capacitive coupling and suppressing the magnetic field by small inductive coupling to maintain low reactance is called self-shielding.
The following formula reflects the law that the current density on the return path under the signal line changes with various conditions:


A conclusion can be drawn from the formula: on the current loop, the closer the position to the signal line, the greater the current density. In this case, the area of the entire loop is the smallest, and the inductance is also the smallest. At the same time, it can be imagined that if the signal line and the loop are very close, the currents of the two are approximately the same, and the directions are opposite. The magnetic fields generated in the external space can cancel each other, so the EMI to the outside world is also very small. Therefore, it is best to ensure that each signal wiring layer has a close ground plane layer corresponding to the stacking arrangement.
Now consider the problem of crosstalk on the ground plane. In high-frequency digital circuits, the main cause of crosstalk is the result of inductive coupling. It can be seen from the above formula of loop current density distribution that when several signal lines are relatively close, the mutual loop currents will overlap. At this time, the magnetic fields between the two will inevitably interfere with each other, which will generate crosstalk noise. The magnitude of the crosstalk voltage is related to the distance D between the signal lines, the height H of the ground plane and the coefficient K, as shown in the figure below:

In the formula, K is related to the rise time of the signal and the length of the signal line that interferes with each other. For the stacked configuration, it is undoubtedly that shortening the distance between the signal layer and the ground layer will effectively reduce the crosstalk of the ground plane.
In the actual PCB layout, such a problem is often encountered. If you do not pay attention to the copper paving of the power supply and the ground layer, an isolated groove may appear in the copper paving area. This situation is often due to vias. It is caused by unreasonable design of isolation area or via hole (as shown in the figure). The consequence is to slow down the rise time and increase the loop area, which leads to an increase in inductance, which is prone to unnecessary crosstalk and EMI. We must avoid this phenomenon.

The increased inductance due to the detour of the loop current can be roughly expressed as:
L=5Dln(D/W)
D represents the vertical distance from the signal line to the nearest end of the broken slot, and W is the line width of the trace.

three. Several typical laminated schemes and analysis
After understanding the above basic knowledge, we can draw the corresponding laminated design plan. In general, try to follow the following rules:

The copper layers should preferably be arranged in pairs. For example, the 2, 5 or 3, 4 layers of the six-layer board should be copper together. This is due to the requirement of balanced structure in the process, because unbalanced copper layers may cause PCB Warpage deformation of the board.
The signal layer and the copper layer should be placed at intervals, and it is best that each signal layer can be adjacent to at least one copper layer.
Shortening the distance between the power supply and the ground layer is conducive to the stability of the power supply and the reduction of EMI.
In the case of very high speed, you can add an extra ground layer to isolate the signal layer, but it is recommended not to add more power layers to isolate, which may cause unnecessary noise interference.
But the actual situation is that the various factors mentioned above cannot be satisfied at the same time. At this time, we must consider a relatively reasonable solution. Several typical laminated design schemes are analyzed below:
First analyze the laminated design of the four-layer board. Generally speaking, for more complex high-speed circuits, it is best not to use a 4-layer board, because it has a number of unstable factors, both in terms of physical and electrical characteristics. If you must design a four-layer board, you can consider setting it as: power-signal-signal-ground. There is a better solution: the outer two layers are both grounded, and the inner
Two-layer power and signal lines are used. This solution is the best stacking solution for four-layer board design. It has an excellent suppression effect on EMI, and it is also very beneficial to reduce the impedance of the signal line. Boards with higher wiring density are more difficult.
The following focuses on the stack design of six-layer boards. Now many circuit boards use 6-layer board technology, such as the design of memory module PCB boards. Most of them use 6-layer boards (high-capacity memory modules may use 10-layer boards. ). The most conventional 6-layer board stack is arranged like this: signal-ground-signal-signal-power-signal. From the point of view of impedance control, this arrangement is reasonable, but because the power supply is far from the ground plane, it is relatively The radiation effect of small common mode EMI is not very good. If you change the copper area to layer 3 and 4, it will cause poor signal impedance control and strong differential mode EMI. There is also a plan to add a ground plane layer, the layout is: signal-ground-signal-power-ground-signal, so that no matter from the perspective of impedance control or from the perspective of reducing EMI, it can achieve the high-speed signal integrity design needs environment. But the disadvantage is that the stacking of layers is unbalanced. The third layer is a signal wiring layer, but the corresponding fourth layer is a power layer with a large area of copper. This may encounter some problems in PCB manufacturing. When designing, all the blank areas on the third layer can be covered with copper to achieve the effect of an approximate balanced structure.
More complex circuit implementation requires the use of ten-layer board technology. The 10-layer PCB board has a very thin insulating dielectric layer, and the signal layer can be very close to the ground plane. This way, the impedance change between layers is very well controlled. Generally, as long as it does not appear With serious stack design errors, designers can easily complete high-quality high-speed circuit board designs. If the wiring is very complicated and requires more wiring layers, we can set the stack as: signal-signal-ground-signal-signal-signal-signal-power-signal-signal, of course this situation is not our best Yes, we require the signal traces to be laid out in a small number of layers, but to isolate other signal layers with redundant ground layers, so the more common stacking scheme is: signal-ground-signal-signal-power-ground-signal- Signal-ground-signal, you can see that three ground plane layers are used here, and only one power supply is used (we only consider the case of a single power supply). This is because although the power layer has the same impedance control effect as the ground plane layer, the voltage on the power layer is subject to greater interference, there are more high-order harmonics, and the EMI to the outside world is also strong, so it goes with the signal. Like the wire layer, it is best to be shielded by the ground plane. At the same time, if an excess power layer is used for isolation, the loop current will have to be converted from the ground plane to the power plane through the decoupling capacitor. In this way, excessive voltage drop on the decoupling capacitor will cause unnecessary noise effects.

Four. Summarize
The above only discusses some of the problems encountered in PCB stack design. The specifics should be determined according to the actual situation. Within the scope of the ability, it is often necessary to take into account the signal quality and cost. While carrying out the design of the laminate scheme in accordance with the theoretical principles described above, we also need to consider some other wiring principles to cooperate, such as the direction of each layer, the definition of the signal layer power line width, and decoupling The placement of capacitors and so on. Only by comprehensively considering various factors can we finally design a circuit board with better performance.

The above is an introduction to the stacking problem of high-speed PCB design. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.