PCB News - PCB power supply decoupling design guide

When engineers design a PCB power distribution system, they first divide the entire design into four parts: power supply (battery, converter or rectifier), PCB, circuit board decoupling capacitors and chip decoupling capacitors. This article will mainly focus on PCB and chip decoupling capacitors. Circuit board decoupling capacitors are usually very large, about 10mF or greater, and are mainly used in specific occasions.

Designing a decoupling capacitor involves two steps. First, calculate the capacitance value based on the electricity, and then place the capacitor on the PCB. To be precise, how far away is the capacitor from the digital chip suitable? But people often overlook that the PCB itself is part of the decoupling design. This article will discuss where the circuit board is suitable for decoupling design.

Decoupling requirements

Basically, the power supply provides energy to the digital chip through a wire. This power supply may be "far" from the chip. It is not uncommon for the power cord to be a 5-inch length of 16 AWG wire and a 4-inch length of 20 mil trace. These wires have resistance, capacitance and induction, all of which affect the transmission of energy. Inductance is directly proportional to the length of the wire and is the cause of most quality problems.

The routing needs to be carefully considered because it determines the total inductance and the loop loop through which the current flows. This loop loop can and is likely to radiate electromagnetic interference (EMI).

Placing a small power supply (such as a capacitor) next to the chip can minimize the length of the trace from the capacitor to the Vcc pin of the chip, thereby reducing the loop area. This can minimize the voltage drop caused by the wire inductance. As the loop loop is reduced, EMI is also reduced.

Connecting the digital chip U1 directly to the power supply means that a few inches of wiring may be required. Capacitor C1 with parasitic inductances L2 and R2 can be inserted into the circuit closer to the chip, the distance is less than 1 inch (Figure 1). L3 is the wire inductance between C1 and U1. L1 and R1 are the parasitic parameters of the wires from the power supply to the capacitor.

In this way, the trace length can be reduced to the mil level, and the wire impedance can be reduced to the extent that it can be applied. C2 is very important here, it determines how much current the power supply must supply. C2 represents the internal load of U1 and the external load that U1 must drive. When S1 is off, these loads are connected to the power source and require current immediately.

Inductance is the main source of impedance between the power supply and the switch. For example, for a 10mil width trace, the resistance, capacitance, and inductance are approximately 0.02Ω/in, 2 pF/in and 20nH/in, respectively. These are typical data for traces (microstrip and stripline) and wires used on PCB boards. When the frequency is approximately higher than 100 kHz, the inductive reactance jΩl is the main impedance.

Therefore, increasing C1 has two effects. One is that it will reduce the guiding inductance between the power supply and the chip during switching. This will protect V1 (that is, Vcc to U1) from decreasing below the voltage required for proper circuit operation. In addition, it can reduce the loop area where high-frequency current flows and the corresponding EMI.

Therefore, the capacitor keeps V1, but how high does it need to keep V1? This problem is mainly focused on the noise margin of the device, such as the minimum voltage noise margin VNmmin, this noise margin can exist and still allow correct circuit operation. (This is a bit difficult to calculate, because the actual value depends on the noise margin of the semiconductor, which is approximately proportional to the power supply voltage.) According to Figure 1, correct operation means that the following conditions need to be met:

VNmmin ≥ VPS? VZmax (1)

In this figure, VZmax falls completely on L3.

The current I also needs to be considered. Simply put, this is the current required by the digital input, and the design engineer must ensure its supply. Because it is the required maximum current, Imax, the maximum impedance Zmax between the power supply and the switch will not be greater than:

|Zmax|≥(VZmax/Imax) (2)

The wiring from the power supply to the chip is a 5-inch-long 16-AWG wire and a 4-inch-long, 20-mil-wide trace, which will provide 100nH inductance. At some frequencies f, the inductive reactance will be greater than the tolerable Zmax. This frequency will be obtained by transforming the impedance equation of the inductor:

fmax = |Zmax|/2πL (3)

Above this frequency, C1 cannot provide enough voltage to meet the noise margin required by the device, and information cannot be successfully transmitted.

The decoupling capacitor provides "high frequency" current for the chips on the PCB board, while the power supply provides "low frequency" current. In order to determine the size of the capacitor, first collect the information needed to calculate fmax. At the fmax frequency, the "low frequency" current supplied by the power source begins to decrease. At the same time, the current required by the U1 load, the voltage to successfully operate these devices, and the conversion time are also required.

In order to obtain these values, the parasitic components of the capacitor need to be considered. In a short time after the conversion occurs, the main power source of U1 is the decoupling capacitor and its parasitic components-equivalent series resistance (ESR) and equivalent series inductance (ESL). ESL includes two parts: wire inductance and capacitor inductance. The former is what design engineers try to minimize, while the latter must be tolerated.

To determine the size of the decoupling capacitor, first determine the capacitive load that the digital N and U1 must drive. This number and the capacitive input of the next chip and the change in voltage over time determine the maximum current required. The current can be determined by the familiar formula I=C*(dV/dt), here:

It is the worst change in voltage during the 0V to VPS transition. Note that when designing the mixed voltage part, use the correct voltage, such as 3.3V/5V.

It is the rise time of the logic device U1 pulse transition. There are many ways to calculate the rise time, so use the worst-case rise time, or the fastest rise time. Now the current pulled down by the load must come from the decoupling capacitor, so use the following formula to calculate the capacitor value:

C=I/(dV/dt) (5)

Although we have now determined the value of the decoupling capacitor, the design has not been completed yet.

Capacitor layout

Next, the design engineer must determine where to place the capacitor on the PCB. It needs to be placed where it can minimize the capacitance and the inductance of the traces between the chips. Inductance also needs to be minimized without trace length. When placing capacitors on the PCB, minimizing the inductance rather than minimizing the trace length will allow more design freedom. First, the design engineer needs to determine the maximum available trace length to maintain maximum design freedom.

The process is as follows: The design engineer needs a capacitor that works from fmax (Eq. 3) to a certain maximum frequency. Determining this upper bound frequency requires understanding the ideal digital waveform output and the necessity of maintaining this shape to a certain degree. This is a small part of signal integrity design.

An ideal digital circuit transmits a rectangular pulse to the next circuit. In fact, rectangular pulses cannot be realized, but trapezoidal pulses can be realized. Check the Fourier sequence of the trapezoidal pulse and find that the trapezoidal pulse is composed of the fundamental frequency and all harmonics. Of course, by adding everything together, the original trapezoidal pulse can be realized.

But what if all the harmonics are not added together? What if only the first 5 or 10 harmonics are added? Are there enough harmonics to create trapezoidal pulses so that the input circuit cannot easily detect changes? Facts have proved that in most cases, just adding the first 10 harmonics can make the recovered waveform fool most circuits, which means that most circuits will not notice changes. This determines the highest frequency that needs to be handled when designing decoupling capacitors. Another suggested method is to use f=1/tr to determine the highest frequency, where tr is the pulse rise time. At this frequency, the harmonic energy is very small and rolls off at a speed of 40dB/decade.

It is now possible to determine the tolerable change in the supply voltage under the worst-case scenario and start the design. For CMOS, this number is the noise preload VOH-VIH (check these values from the data sheet). The worst-case changes are:

V = VCC(nominal)-(VOH+10%*VCC) (6)

10% is the drop factor of the power supply.

Using equation 6 and the inductor current and voltage, determine the maximum allowable inductance L:

L=V/(dI/dt) (7)

Among them, L is the total series inductance introduced by capacitors, traces, chip connecting wires and leads, etc., dI is the maximum current change, and dt is the rise time of the current.

Trace length

For two or more capacitors, their parallel connection to the power input pins of the chip has different trace lengths. The effective trace length determines how far away the capacitor can be placed. The length of the trace is directly related to the inductance of the trace. Therefore, the effective trace length can be obtained through the formula of parallel inductance, and the effective trace length IE is:

IE=(I1*I2)/(I1+I2) (8)

Among them, I1 and I2 are the trace lengths of parallel capacitors. The maximum distance of each parallel capacitor from the VCC pin is IE.

Once the capacitor is selected and placed on the PCB, it is necessary to check where the capacitance and parasitic inductance will appear. The resonance frequency can be obtained by the following formula:

f=1/2π=π√-LC (9)

Where L=IE SL + LTRACE.

Above this frequency, the capacitor quickly becomes an inductance. If the resonance frequency occurs at a frequency much lower than 10 * fpulse, check the design to take compromise measures.

Use multiple decoupling capacitors

If N capacitors with the same capacitance value are used, the total ESL and ESR will be reduced to 1/N (Figure 2). This is a special case when the traces connecting the capacitors between the power supply and the ground are equal. It is also assumed that the mutual coupling between the inductors is small. The impedance curve of N capacitors with the same capacitance value is close to the curve of a single capacitor.

If N capacitors with different capacitance values are used, ESR and ESL will be reduced, but a resonance peak will be introduced in the impedance curve, and will bring serious design consequences (Figure 3). Here again, it is assumed that the trace lengths are the same.

Use PCB

Don't forget the PCB. Ignoring the many benefits it provides almost free of charge will increase design costs and add additional components. These additional components will take up additional space, reduce overall reliability and possibly increase EMI.

Equation 10 gives the impedance formula for a set of parallel power planes. This is just the impedance formula of the series LRC circuit. As long as the PCB does not start to work like a transmission line, this formula is useful. In other words, if l<λ/20, then it is useful. Where l is the maximum size of the PCB (diagonal), and λ is the wavelength related to the highest frequency.

Up to this point, the PCB impedance is almost capacitive and can provide all the required current above the cut-off frequency of the coupling capacitor. Because the ESR is very small and the parasitic inductance is also very small, the PCB will exhibit very low impedance in a relatively wide frequency range.

If the PCB has two adjacent power and ground planes, then it has good internal capacitance in the design. The calculation formula for parallel plane capacitance can be used to determine the capacitance of the PCB:

C(pF)=ε(A/d)=0.225(εr /d)A (11)

The last part of the above formula is valid when measured in inches. Among them, ε = ε0*εr, ε0 is the dielectric constant of air, which is 8.85 pF/m, and er is the relative dielectric constant of the medium between the capacitor plates. For FR4 materials, er is equal to 4.5. A is the area between the capacitor plates, and d is the distance between the plates.

In fact, there is no upper frequency limit for the ability of the PCB to input current to the VCC pin. PCB design is a complicated subject, and there are many available media to increase the upper limit frequency. For FR4 materials, the upper limit frequency range is very high, exceeding 2 GHz, which makes most automotive PCB circuits look like the upper limit frequency is unlimited. In fact, the upper limit frequency is determined by the maximum size l and the minimum wavelength λ of the PCB.

Unfortunately, the total capacitance of the PCB is very small in automatic design. When FR4 is used as the dielectric, the board spacing is 20 mils, and there are fixed power and ground plane capacitances, the PCB capacitance is usually about 53 pF/square inch. A 4-layer FR4 PCB will have a certain range of dielectric thickness. This change can come from process changes, the required thickness of the entire board, the required elasticity or hardness, the copper thickness (which affects the dielectric thickness), and the breakdown voltage requirements. Without special requirements, the PCB dielectric thickness varies from 0.5 to 0.8mm.

The quality of PCB capacitors is usually very good, because there is very little inductance. As mentioned earlier, inductance is the main cause of capacitor degradation with frequency.

The small size of the capacitor is a factor worth noting. The capacitance value that can effectively supply current on the PCB generally exceeds 500 pF/square inch. It is impossible to obtain this value on the FR4 board, so special PCB design and materials are required.

EMC benefits

In addition to the signal integrity gained from a well-designed power distribution system, PCBs will also bring lower EMI. As mentioned earlier, this is mainly due to the reduced loop area. This is manifested in two ways. First, Faraday's law states that the loop area A will bring voltage to the circuit through the current flowing through other circuits.

VINDUCED(V)=[(?AN/2πd)*(dI/dt)*cos(θ) (12)

Similarly, in digital circuits, the simplified expression of the electromagnetic field caused by the current loop shows that the smaller loop has lower radiation:

E(V/m)=263*10-16*[f2A(I/r)] (13)

Cost-effectiveness

A well-designed power distribution system can save costs. Equation 14 gives a simple relationship between device reduction and cost reduction.

So far, the discussion revolved around providing current to the chip. But the designer may wish to limit the current flowing to the chip. Remember, a chip can work well as long as it has a current lower than the upper limit frequency (10 * fmax), or 1/πtr. The designer cannot touch any currents at those frequencies. But beyond a certain upper frequency, the chip can work well without current. In addition, because those currents may generate EMI, they can be suppressed, thereby reducing EMI.

The above is an introduction to the PCB power supply decoupling design guide. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.