PCB News - Power Integrity Design in PCB Circuit

In PCB design, we generally care about the quality of the signal, but sometimes we often confine ourselves to the signal line for research, and treat the power and ground as ideal conditions. Although this can simplify the problem, it is in high-speed design. In China, this simplification is no longer feasible. Although the more direct result of circuit design is shown in signal integrity, we must not neglect the power integrity design. Because power integrity directly affects the signal integrity of the final PCB board. Power integrity and signal integrity are closely related, and in many cases, the main cause of signal distortion is the power system. For example, the ground bounce noise is too large, the design of the decoupling capacitor is not suitable, the loop influence is very serious, the division of multiple power/ground planes is not good, the ground layer design is unreasonable, the current is uneven, and so on.

1) Power distribution system

Power integrity design is a very complicated matter, but how to control the impedance between the power system (power and ground plane) in recent years is the key to the design. In theory, the lower the impedance between power systems, the better, the lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In actual design, we can determine the target impedance we hope to achieve by specifying the maximum voltage and power supply range, and then, by adjusting the relevant factors in the circuit, the impedance of each part of the power system (related to frequency) is approached to the target impedance.

2) Ground bounce

When the edge rate of the high-speed device is lower than 0.5ns, the data exchange rate from the large-capacity data bus is extremely fast. When it generates strong ripples in the power layer that can affect the signal, the problem of power instability will occur. When the current through the ground loop changes, a voltage is generated due to the loop inductance. When the rising edge is shortened, the current change rate increases and the ground bounce voltage increases. At this time, the ground plane (ground) is no longer an ideal zero level, and the power supply is not an ideal DC potential. When the number of gates that are switched at the same time increases, the ground bounce becomes more serious. For a 128-bit bus, there may be 50-100 I/O lines switching on the same clock edge. At this time, the inductance of the power and ground loops fed back to the I/O driver that is switched at the same time must be as low as possible, otherwise, a voltage brush will appear when connected to the same ground at rest. Ground bounce can be seen everywhere, such as chips, packages, connectors, or circuit boards, which may cause ground bounce, causing power integrity problems.

From the perspective of technological development, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to keep ground bounce at an acceptable level is to reduce the power and ground distribution inductance. For the chip, it means moving to an array chip, placing as many power and ground as possible, and connecting the wiring to the package as short as possible to reduce inductance. For packaging, it means moving layer packaging to make the distance between the power ground planes closer, as used in BGA packaging. For the connector, it means using more ground pins or redesigning the connector to have an internal power supply and ground plane, such as a connector-based ribbon cord. For the circuit board, it means making the adjacent power and ground planes as close as possible. Since the inductance is proportional to the length, making the connection between the power supply and the ground as short as possible will reduce ground noise.

3) Decoupling capacitor

We all know that adding some capacitors between the power supply and the ground can reduce the noise of the system, but how many capacitors should be added on the circuit board? What is the appropriate value of each capacitor? What position is better for each capacitor? Similar to these questions We generally don't think about it seriously, but do it based on the designer's experience, and sometimes even think that the less capacitance the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors, the capacitance value of each capacitor and the specific location of the placement, to ensure that the impedance of the system is within the control range, a basic principle It is the required decoupling capacitor, none of which is missing, and no excess capacitors.

The above is the introduction of power integrity design in PCB circuits. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.